Vamsi K Vytla 5f9cd2e2f6 Preserve 'signed'-ness of a verilog wire through RTLIL ... As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser		2020-04-27 09:44:24 -07:00
..
Makefile.inc	Added JSON backend	2015-03-02 23:30:58 +01:00
json.cc	Preserve 'signed'-ness of a verilog wire through RTLIL	2020-04-27 09:44:24 -07:00