mirror of https://github.com/YosysHQ/yosys.git
17 lines
298 B
Verilog
17 lines
298 B
Verilog
// Like flow.v, but results in a network identical to Figure 2(b).
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module top(...);
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input a,b,c,d,e,f;
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wire A = b&c;
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wire B = c|d;
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wire C = e&f;
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wire D = A|B;
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wire E = a&D;
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wire F = D&C;
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wire G = F|B;
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wire H = a&F;
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wire I = E|G;
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wire J = G&C;
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output p = H&I;
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output q = A|J;
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endmodule
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