yosys/passes
Eddie Hung 2b93b8fc74
Merge pull request #1374 from YosysHQ/eddie/fix1371
Fix two non-deterministic behaviours that cause divergence between compilers
2019-09-15 13:56:07 -07:00
..
cmds Revert "SigSet<Cell*> to use stable compare class" 2019-09-13 09:49:15 -07:00
equiv Add equiv_opt -multiclock 2019-09-11 13:55:59 +01:00
fsm RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
hierarchy Adopt @cliffordwolf's suggestion 2019-09-03 12:18:50 -07:00
memory stoi -> atoi 2019-08-07 11:09:17 -07:00
opt Revert "SigSet<Cell*> to use stable compare class" 2019-09-13 09:49:15 -07:00
pmgen Fix misspelling 2019-09-09 16:46:33 -07:00
proc proc_clean: fix order of switch insertion. 2019-08-19 16:44:23 +00:00
sat Revert "SigSet<Cell*> to use stable compare class" 2019-09-13 09:49:15 -07:00
techmap Explicitly order function arguments 2019-09-13 16:18:05 -07:00
tests More use of IdString::in() 2019-08-15 09:23:57 -07:00