mirror of https://github.com/YosysHQ/yosys.git
294 lines
8.2 KiB
C++
294 lines
8.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef CELLTYPES_H
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#define CELLTYPES_H
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#include <set>
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#include <string>
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#include <stdlib.h>
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#include <kernel/rtlil.h>
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#include <kernel/log.h>
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struct CellTypes
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{
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std::set<std::string> cell_types;
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std::vector<const RTLIL::Design*> designs;
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CellTypes()
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{
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}
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CellTypes(const RTLIL::Design *design)
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{
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setup(design);
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}
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void setup(const RTLIL::Design *design = NULL)
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{
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if (design)
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setup_design(design);
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setup_internals();
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setup_internals_mem();
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setup_stdcells();
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setup_stdcells_mem();
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}
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void setup_design(const RTLIL::Design *design)
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{
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designs.push_back(design);
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}
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void setup_internals()
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{
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cell_types.insert("$not");
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cell_types.insert("$pos");
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cell_types.insert("$neg");
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cell_types.insert("$and");
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cell_types.insert("$or");
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cell_types.insert("$xor");
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cell_types.insert("$xnor");
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cell_types.insert("$reduce_and");
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cell_types.insert("$reduce_or");
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cell_types.insert("$reduce_xor");
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cell_types.insert("$reduce_xnor");
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cell_types.insert("$reduce_bool");
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cell_types.insert("$shl");
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cell_types.insert("$shr");
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cell_types.insert("$sshl");
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cell_types.insert("$sshr");
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cell_types.insert("$lt");
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cell_types.insert("$le");
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cell_types.insert("$eq");
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cell_types.insert("$ne");
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cell_types.insert("$ge");
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cell_types.insert("$gt");
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cell_types.insert("$add");
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cell_types.insert("$sub");
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cell_types.insert("$mul");
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cell_types.insert("$div");
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cell_types.insert("$mod");
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cell_types.insert("$pow");
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cell_types.insert("$logic_not");
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cell_types.insert("$logic_and");
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cell_types.insert("$logic_or");
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cell_types.insert("$mux");
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cell_types.insert("$pmux");
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cell_types.insert("$safe_pmux");
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cell_types.insert("$lut");
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}
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void setup_internals_mem()
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{
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cell_types.insert("$sr");
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cell_types.insert("$dff");
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cell_types.insert("$dffsr");
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cell_types.insert("$adff");
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cell_types.insert("$dlatch");
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cell_types.insert("$memrd");
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cell_types.insert("$memwr");
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cell_types.insert("$mem");
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cell_types.insert("$fsm");
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}
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void setup_stdcells()
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{
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cell_types.insert("$_INV_");
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cell_types.insert("$_AND_");
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cell_types.insert("$_OR_");
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cell_types.insert("$_XOR_");
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cell_types.insert("$_MUX_");
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}
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void setup_stdcells_mem()
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{
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cell_types.insert("$_SR_NN_");
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cell_types.insert("$_SR_NP_");
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cell_types.insert("$_SR_PN_");
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cell_types.insert("$_SR_PP_");
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cell_types.insert("$_DFF_N_");
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cell_types.insert("$_DFF_P_");
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cell_types.insert("$_DFF_NN0_");
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cell_types.insert("$_DFF_NN1_");
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cell_types.insert("$_DFF_NP0_");
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cell_types.insert("$_DFF_NP1_");
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cell_types.insert("$_DFF_PN0_");
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cell_types.insert("$_DFF_PN1_");
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cell_types.insert("$_DFF_PP0_");
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cell_types.insert("$_DFF_PP1_");
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cell_types.insert("$_DFFSR_NNN_");
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cell_types.insert("$_DFFSR_NNP_");
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cell_types.insert("$_DFFSR_NPN_");
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cell_types.insert("$_DFFSR_NPP_");
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cell_types.insert("$_DFFSR_PNN_");
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cell_types.insert("$_DFFSR_PNP_");
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cell_types.insert("$_DFFSR_PPN_");
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cell_types.insert("$_DFFSR_PPP_");
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cell_types.insert("$_DLATCH_N_");
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cell_types.insert("$_DLATCH_P_");
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}
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void clear()
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{
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cell_types.clear();
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designs.clear();
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}
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bool cell_known(std::string type)
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{
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if (cell_types.count(type) > 0)
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return true;
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for (auto design : designs)
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if (design->modules.count(type) > 0)
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return true;
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return false;
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}
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bool cell_output(std::string type, std::string port)
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{
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if (cell_types.count(type) == 0) {
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for (auto design : designs)
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if (design->modules.count(type) > 0) {
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if (design->modules.at(type)->wires.count(port))
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return design->modules.at(type)->wires.at(port)->port_output;
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return false;
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}
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return false;
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}
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if (port == "\\Y" || port == "\\Q" || port == "\\RD_DATA")
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return true;
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if (type == "$memrd" && port == "\\DATA")
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return true;
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if (type == "$fsm" && port == "\\CTRL_OUT")
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return true;
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if (type == "$lut" && port == "\\O")
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return true;
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return false;
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}
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bool cell_input(std::string type, std::string port)
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{
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if (cell_types.count(type) == 0) {
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for (auto design : designs)
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if (design->modules.count(type) > 0) {
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if (design->modules.at(type)->wires.count(port))
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return design->modules.at(type)->wires.at(port)->port_input;
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return false;
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}
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return false;
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}
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if (cell_types.count(type) > 0)
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return !cell_output(type, port);
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return false;
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}
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static RTLIL::Const eval(std::string type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
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{
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if (type == "$sshr" && !signed1)
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type = "$shr";
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if (type == "$sshl" && !signed1)
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type = "$shl";
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if (type != "$sshr" && type != "$sshl" && type != "$shr" && type != "$shl" &&
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type != "$pos" && type != "$neg" && type != "$not") {
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if (!signed1 || !signed2)
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signed1 = false, signed2 = false;
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}
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#define HANDLE_CELL_TYPE(_t) if (type == "$" #_t) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);
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HANDLE_CELL_TYPE(not)
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HANDLE_CELL_TYPE(and)
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HANDLE_CELL_TYPE(or)
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HANDLE_CELL_TYPE(xor)
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HANDLE_CELL_TYPE(xnor)
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HANDLE_CELL_TYPE(reduce_and)
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HANDLE_CELL_TYPE(reduce_or)
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HANDLE_CELL_TYPE(reduce_xor)
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HANDLE_CELL_TYPE(reduce_xnor)
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HANDLE_CELL_TYPE(reduce_bool)
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HANDLE_CELL_TYPE(logic_not)
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HANDLE_CELL_TYPE(logic_and)
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HANDLE_CELL_TYPE(logic_or)
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HANDLE_CELL_TYPE(shl)
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HANDLE_CELL_TYPE(shr)
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HANDLE_CELL_TYPE(sshl)
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HANDLE_CELL_TYPE(sshr)
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HANDLE_CELL_TYPE(lt)
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HANDLE_CELL_TYPE(le)
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HANDLE_CELL_TYPE(eq)
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HANDLE_CELL_TYPE(ne)
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HANDLE_CELL_TYPE(ge)
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HANDLE_CELL_TYPE(gt)
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HANDLE_CELL_TYPE(add)
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HANDLE_CELL_TYPE(sub)
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HANDLE_CELL_TYPE(mul)
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HANDLE_CELL_TYPE(div)
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HANDLE_CELL_TYPE(mod)
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HANDLE_CELL_TYPE(pow)
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HANDLE_CELL_TYPE(pos)
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HANDLE_CELL_TYPE(neg)
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#undef HANDLE_CELL_TYPE
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if (type == "$_INV_")
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return const_not(arg1, arg2, false, false, 1);
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if (type == "$_AND_")
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return const_and(arg1, arg2, false, false, 1);
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if (type == "$_OR_")
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return const_or(arg1, arg2, false, false, 1);
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if (type == "$_XOR_")
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return const_xor(arg1, arg2, false, false, 1);
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log_abort();
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}
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static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2)
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{
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bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool();
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bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool();
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int result_len = cell->parameters.count("\\Y_WIDTH") > 0 ? cell->parameters["\\Y_WIDTH"].as_int() : -1;
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return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len);
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}
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static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &sel)
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{
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if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_") {
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RTLIL::Const ret = arg1;
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for (size_t i = 0; i < sel.bits.size(); i++)
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if (sel.bits[i] == RTLIL::State::S1) {
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std::vector<RTLIL::State> bits(arg2.bits.begin() + i*arg1.bits.size(), arg2.bits.begin() + (i+1)*arg1.bits.size());
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ret = RTLIL::Const(bits);
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}
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return ret;
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}
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assert(sel.bits.size() == 0);
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bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool();
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bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool();
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int result_len = cell->parameters.count("\\Y_WIDTH") > 0 ? cell->parameters["\\Y_WIDTH"].as_int() : -1;
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return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len);
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}
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};
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#endif
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