mirror of https://github.com/YosysHQ/yosys.git
34 lines
762 B
Plaintext
34 lines
762 B
Plaintext
bram MISTRAL_M10K
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init 0 # TODO: Re-enable when I figure out how BRAM init works
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abits 13 @D8192x1
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dbits 1 @D8192x1
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abits 12 @D4096x2
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dbits 2 @D4096x2
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abits 11 @D2048x4 @D2048x5
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dbits 4 @D2048x4
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dbits 5 @D2048x5
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abits 10 @D1024x8 @D1024x10
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dbits 8 @D1024x8
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dbits 10 @D1024x10
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abits 9 @D512x16 @D512x20
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dbits 16 @D512x16
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dbits 20 @D512x20
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abits 8 @D256x32 @D256x40
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dbits 32 @D256x32
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dbits 40 @D256x40
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groups 2
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ports 1 1
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wrmode 1 0
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# read enable; write enable + byte enables (only for multiples of 8)
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enable 1 1
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transp 0 0
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clocks 1 1
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clkpol 1 1
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endbram
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match MISTRAL_M10K
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min efficiency 5
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make_transp
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endmatch
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