mirror of https://github.com/YosysHQ/yosys.git
124 lines
4.6 KiB
C++
124 lines
4.6 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2019 Marcin Kościelnicki <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void split_portname_pair(std::string &port1, std::string &port2)
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{
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size_t pos = port1.find_first_of(':');
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if (pos != std::string::npos) {
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port2 = port1.substr(pos+1);
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port1 = port1.substr(0, pos);
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}
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}
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struct ExtractinvPass : public Pass {
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ExtractinvPass() : Pass("extractinv", "extract explicit inverter cells for invertible cell pins") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" extractinv [options] [selection]\n");
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log("\n");
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log("Searches the design for all cells with invertible pins controlled by a cell\n");
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log("parameter (eg. IS_CLK_INVERTED on many Xilinx cells) and removes the parameter.\n");
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log("If the parameter was set to 1, inserts an explicit inverter cell in front of\n");
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log("the pin instead. Normally used for output to ISE, which does not support the\n");
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log("inversion parameters.\n");
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log("\n");
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log("To mark a cell port as invertible, use (* invertible_pin = \"param_name\" *)\n");
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log("on the wire in the blackbox module. The parameter value should have\n");
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log("the same width as the port, and will be effectively XORed with it.\n");
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log("\n");
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log(" -inv <celltype> <portname_out>:<portname_in>\n");
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log(" Specifies the cell type to use for the inverters and its port names.\n");
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log(" This option is required.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing EXTRACTINV pass (extracting pin inverters).\n");
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std::string inv_celltype, inv_portname, inv_portname2;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-inv" && argidx+2 < args.size()) {
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inv_celltype = args[++argidx];
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inv_portname = args[++argidx];
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split_portname_pair(inv_portname, inv_portname2);
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (inv_celltype.empty())
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log_error("The -inv option is required.\n");
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for (auto module : design->selected_modules())
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{
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for (auto cell : module->selected_cells())
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for (auto port : cell->connections()) {
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auto cell_module = design->module(cell->type);
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if (!cell_module)
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continue;
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auto cell_wire = cell_module->wire(port.first);
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if (!cell_wire)
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continue;
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auto it = cell_wire->attributes.find(ID::invertible_pin);
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if (it == cell_wire->attributes.end())
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continue;
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IdString param_name = RTLIL::escape_id(it->second.decode_string());
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auto it2 = cell->parameters.find(param_name);
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// Inversion not used -- skip.
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if (it2 == cell->parameters.end())
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continue;
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SigSpec sig = port.second;
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if (it2->second.size() != sig.size())
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log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", log_id(module->name), log_id(cell->type), log_id(port.first), log_id(param_name));
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RTLIL::Const invmask = it2->second;
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cell->parameters.erase(param_name);
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if (invmask.is_fully_zero())
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continue;
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Wire *iwire = module->addWire(NEW_ID, sig.size());
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for (int i = 0; i < sig.size(); i++)
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if (invmask[i] == State::S1) {
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RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype));
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icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i));
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icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]);
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log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype.c_str(), log_id(module), log_id(cell->type), log_id(port.first), i);
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sig[i] = SigBit(iwire, i);
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}
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cell->setPort(port.first, sig);
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}
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}
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}
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} ExtractinvPass;
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PRIVATE_NAMESPACE_END
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