mirror of https://github.com/YosysHQ/yosys.git
e97e33d00d
Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs. |
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.. | ||
.gitignore | ||
Makefile.inc | ||
const2ast.cc | ||
preproc.cc | ||
verilog_frontend.cc | ||
verilog_frontend.h | ||
verilog_lexer.l | ||
verilog_parser.y |