yosys/techlibs
Clifford Wolf 023086bd46 Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 04:47:55 +02:00
..
achronix Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
anlogic Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
common Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 2019-08-06 04:47:55 +02:00
coolrunner2 Unify usage of noflatten among architectures 2019-01-04 11:37:25 +01:00
easic Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
ecp5 synth_ecp5: rename dram to lutram everywhere. 2019-07-16 20:45:12 +00:00
gowin Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
greenpak4 techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module 2019-02-26 09:40:46 -08:00
ice40 ice40: Fix test_dsp_model.sh 2019-07-19 17:33:57 +01:00
intel Merge branch 'ZirconiumX-synth_intel_m9k' 2019-07-25 17:23:48 +02:00
sf2 Add link to SF2 / igloo2 macro library guide 2019-03-07 09:08:26 -08:00
xilinx RST -> RSTBRST for RAMB8BWER 2019-07-29 16:05:44 -07:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00