yosys/techlibs
Clifford Wolf 1202f7aa4b Renamed "stdcells.v" to "techmap.v" 2014-07-31 02:32:00 +02:00
..
cmos
common Renamed "stdcells.v" to "techmap.v" 2014-07-31 02:32:00 +02:00
xilinx
.gitignore