mirror of https://github.com/YosysHQ/yosys.git
300 lines
8.6 KiB
C++
300 lines
8.6 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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#include "kernel/celltypes.h"
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#include "fsmdata.h"
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#include <string.h>
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struct FsmOpt
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{
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FsmData fsm_data;
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RTLIL::Cell *cell;
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RTLIL::Module *module;
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bool signal_is_unused(RTLIL::SigSpec sig)
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{
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RTLIL::SigBit bit = sig.to_single_sigbit();
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if (bit.wire == NULL || bit.wire->attributes.count("\\unused_bits") == 0)
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return false;
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char *str = strdup(bit.wire->attributes["\\unused_bits"].decode_string().c_str());
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for (char *tok = strtok(str, " "); tok != NULL; tok = strtok(NULL, " ")) {
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if (tok[0] && bit.offset == atoi(tok)) {
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free(str);
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return true;
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}
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}
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free(str);
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return false;
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}
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void opt_const_and_unused_inputs()
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{
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RTLIL::SigSpec ctrl_in = cell->getPort("\\CTRL_IN");
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std::vector<bool> ctrl_in_used(ctrl_in.size());
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std::vector<FsmData::transition_t> new_transition_table;
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for (auto &tr : fsm_data.transition_table) {
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for (int i = 0; i < ctrl_in.size(); i++) {
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RTLIL::SigSpec ctrl_bit = ctrl_in.extract(i, 1);
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if (ctrl_bit.is_fully_const()) {
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if (tr.ctrl_in.bits[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in.bits[i]) != ctrl_bit)
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goto delete_this_transition;
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continue;
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}
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if (tr.ctrl_in.bits[i] <= RTLIL::State::S1)
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ctrl_in_used[i] = true;
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}
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new_transition_table.push_back(tr);
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delete_this_transition:;
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}
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for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) {
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if (!ctrl_in_used[i]) {
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log(" Removing unused input signal %s.\n", log_signal(cell->getPort("\\CTRL_IN").extract(i, 1)));
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for (auto &tr : new_transition_table) {
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RTLIL::SigSpec tmp(tr.ctrl_in);
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tmp.remove(i, 1);
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tr.ctrl_in = tmp.as_const();
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}
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RTLIL::SigSpec new_ctrl_in = cell->getPort("\\CTRL_IN");
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new_ctrl_in.remove(i, 1);
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cell->setPort("\\CTRL_IN", new_ctrl_in);
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fsm_data.num_inputs--;
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}
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}
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fsm_data.transition_table.swap(new_transition_table);
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new_transition_table.clear();
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}
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void opt_unused_outputs()
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{
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for (int i = 0; i < fsm_data.num_outputs; i++) {
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RTLIL::SigSpec sig = cell->getPort("\\CTRL_OUT").extract(i, 1);
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if (signal_is_unused(sig)) {
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log(" Removing unused output signal %s.\n", log_signal(sig));
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RTLIL::SigSpec new_ctrl_out = cell->getPort("\\CTRL_OUT");
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new_ctrl_out.remove(i, 1);
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cell->setPort("\\CTRL_OUT", new_ctrl_out);
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for (auto &tr : fsm_data.transition_table) {
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RTLIL::SigSpec tmp(tr.ctrl_out);
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tmp.remove(i, 1);
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tr.ctrl_out = tmp.as_const();
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}
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fsm_data.num_outputs--;
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i--;
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}
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}
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}
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void opt_alias_inputs()
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{
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RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"];
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for (int i = 0; i < ctrl_in.size(); i++)
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for (int j = i+1; j < ctrl_in.size(); j++)
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if (ctrl_in.extract(i, 1) == ctrl_in.extract(j, 1))
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{
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log(" Optimize handling of signal %s that is connected to inputs %d and %d.\n", log_signal(ctrl_in.extract(i, 1)), i, j);
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std::vector<FsmData::transition_t> new_transition_table;
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for (auto tr : fsm_data.transition_table)
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{
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RTLIL::State &si = tr.ctrl_in.bits[i];
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RTLIL::State &sj = tr.ctrl_in.bits[j];
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if (si > RTLIL::State::S1)
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si = sj;
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else if (sj > RTLIL::State::S1)
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sj = si;
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if (si == sj) {
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RTLIL::SigSpec tmp(tr.ctrl_in);
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tmp.remove(j, 1);
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tr.ctrl_in = tmp.as_const();
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new_transition_table.push_back(tr);
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}
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}
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ctrl_in.remove(j--, 1);
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fsm_data.num_inputs--;
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fsm_data.transition_table.swap(new_transition_table);
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new_transition_table.clear();
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}
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}
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void opt_feedback_inputs()
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{
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RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"];
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RTLIL::SigSpec &ctrl_out = cell->connections_["\\CTRL_OUT"];
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for (int j = 0; j < ctrl_out.size(); j++)
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for (int i = 0; i < ctrl_in.size(); i++)
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if (ctrl_in.extract(i, 1) == ctrl_out.extract(j, 1))
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{
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log(" Optimize handling of signal %s that is connected to input %d and output %d.\n", log_signal(ctrl_in.extract(i, 1)), i, j);
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std::vector<FsmData::transition_t> new_transition_table;
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for (auto tr : fsm_data.transition_table)
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{
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RTLIL::State &si = tr.ctrl_in.bits[i];
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RTLIL::State &sj = tr.ctrl_out.bits[j];
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if (si > RTLIL::State::S1 || si == sj) {
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RTLIL::SigSpec tmp(tr.ctrl_in);
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tmp.remove(i, 1);
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tr.ctrl_in = tmp.as_const();
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new_transition_table.push_back(tr);
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}
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}
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ctrl_in.remove(i--, 1);
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fsm_data.num_inputs--;
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fsm_data.transition_table.swap(new_transition_table);
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new_transition_table.clear();
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}
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}
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void opt_find_dont_care_worker(std::set<RTLIL::Const> &set, int bit, FsmData::transition_t &tr, bool &did_something)
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{
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std::set<RTLIL::Const> new_set;
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for (auto &pattern : set)
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{
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if (pattern.bits[bit] > RTLIL::State::S1) {
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new_set.insert(pattern);
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continue;
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}
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RTLIL::Const other_pattern = pattern;
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if (pattern.bits[bit] == RTLIL::State::S1)
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other_pattern.bits[bit] = RTLIL::State::S0;
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else
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other_pattern.bits[bit] = RTLIL::State::S1;
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if (set.count(other_pattern) > 0) {
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log(" Merging pattern %s and %s from group (%d %d %s).\n", log_signal(pattern), log_signal(other_pattern),
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tr.state_in, tr.state_out, log_signal(tr.ctrl_out));
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other_pattern.bits[bit] = RTLIL::State::Sa;
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new_set.insert(other_pattern);
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did_something = true;
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continue;
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}
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new_set.insert(pattern);
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}
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set.swap(new_set);
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}
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void opt_find_dont_care()
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{
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typedef std::pair<std::pair<int, int>, RTLIL::Const> group_t;
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std::map<group_t, std::set<RTLIL::Const>> transitions_by_group;
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for (auto &tr : fsm_data.transition_table) {
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group_t group(std::pair<int, int>(tr.state_in, tr.state_out), tr.ctrl_out);
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transitions_by_group[group].insert(tr.ctrl_in);
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}
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fsm_data.transition_table.clear();
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for (auto &it : transitions_by_group)
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{
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FsmData::transition_t tr;
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tr.state_in = it.first.first.first;
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tr.state_out = it.first.first.second;
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tr.ctrl_out = it.first.second;
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bool did_something = true;
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while (did_something) {
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did_something = false;
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for (int i = 0; i < fsm_data.num_inputs; i++)
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opt_find_dont_care_worker(it.second, i, tr, did_something);
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}
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for (auto &ci : it.second) {
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tr.ctrl_in = ci;
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fsm_data.transition_table.push_back(tr);
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}
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}
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}
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FsmOpt(RTLIL::Cell *cell, RTLIL::Module *module)
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{
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log("Optimizing FSM `%s' from module `%s'.\n", cell->name.c_str(), module->name.c_str());
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fsm_data.copy_from_cell(cell);
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this->cell = cell;
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this->module = module;
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opt_unused_outputs();
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opt_alias_inputs();
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opt_feedback_inputs();
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opt_find_dont_care();
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opt_const_and_unused_inputs();
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fsm_data.copy_to_cell(cell);
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}
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};
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void FsmData::optimize_fsm(RTLIL::Cell *cell, RTLIL::Module *module)
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{
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FsmOpt fsmopt(cell, module);
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}
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struct FsmOptPass : public Pass {
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FsmOptPass() : Pass("fsm_opt", "optimize finite state machines") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" fsm_opt [selection]\n");
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log("\n");
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log("This pass optimizes FSM cells. It detects which output signals are actually\n");
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log("not used and removes them from the FSM. This pass is usually used in\n");
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log("combination with the 'opt_clean' pass (see also 'help fsm').\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing FSM_OPT pass (simple optimizations of FSMs).\n");
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules_) {
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if (design->selected(mod_it.second))
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for (auto &cell_it : mod_it.second->cells_)
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if (cell_it.second->type == "$fsm" and design->selected(mod_it.second, cell_it.second))
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FsmData::optimize_fsm(cell_it.second, mod_it.second);
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}
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}
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} FsmOptPass;
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