yosys/tests/functional/single_cells/rtlil/test_cell_sop_00000.il

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# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
autoidx 1
module \gold
wire width 8 input 1 \A
wire output 2 \Y
cell $sop \UUT
parameter \DEPTH 8
parameter \TABLE 128'10010000100100000101101010001001101000101010010100010000010100000101010100000001001010010110101010101010101000100100011001000110
parameter \WIDTH 8
connect \A \A
connect \Y \Y
end
end