yosys/tests/functional/single_cells/rtlil/test_cell_pos_00000.il

# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
autoidx 1
module \gold
  wire input 1 \A
  wire width 3 output 2 \Y
  cell $pos \UUT
    parameter \A_SIGNED 1
    parameter \A_WIDTH 1
    parameter \Y_WIDTH 3
    connect \A \A
    connect \Y \Y
  end
end