yosys/tests/functional/single_cells/rtlil/test_cell_neg_00000.il

# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
autoidx 1
module \gold
  wire width 2 input 1 \A
  wire width 5 output 2 \Y
  cell $neg \UUT
    parameter \A_SIGNED 0
    parameter \A_WIDTH 2
    parameter \Y_WIDTH 5
    connect \A \A
    connect \Y \Y
  end
end