yosys/tests/functional/single_cells/rtlil/test_cell_lt_00000.il

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# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
autoidx 1
module \gold
wire width 8 input 1 \A
wire width 5 input 2 \B
wire width 6 output 3 \Y
cell $lt \UUT
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 6
connect \A \A
connect \B \B
connect \Y \Y
end
end