yosys/tests/functional/single_cells/rtlil/test_cell_fa_00000.il

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# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os)
autoidx 1
module \gold
wire input 1 \A
wire input 2 \B
wire input 3 \C
wire output 4 \X
wire output 5 \Y
cell $fa \UUT
parameter \WIDTH 1
connect \A \A
connect \B \B
connect \C \C
connect \X \X
connect \Y \Y
end
end