mirror of https://github.com/YosysHQ/yosys.git
116 lines
2.9 KiB
Verilog
116 lines
2.9 KiB
Verilog
module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 10;
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parameter CFG_DBITS = 18;
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parameter CFG_ENABLE_A = 2;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [18431:0] INIT = 18432'bx;
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parameter TRANSP2 = 0;
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input CLK2;
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input CLK3;
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input [CFG_ABITS-1:0] A1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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input [CFG_ENABLE_A-1:0] A1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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output [CFG_DBITS-1:0] B1DATA;
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input B1EN;
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localparam CLKAMUX = CLKPOL2 ? "CLKA" : "INV";
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localparam CLKBMUX = CLKPOL3 ? "CLKB" : "INV";
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localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE";
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generate if (CFG_DBITS == 1) begin
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DP16KD #(
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`include "bram_init_1_2_4.vh"
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.DATA_WIDTH_A(1),
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.DATA_WIDTH_B(1),
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.CLKAMUX(CLKAMUX),
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.CLKBMUX(CLKBMUX),
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.WRITEMODE_A(WRITEMODE_A),
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.WRITEMODE_B("READBEFOREWRITE"),
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.GSR("DISABLED")
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) _TECHMAP_REPLACE_ (
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`include "bram_conn_1.vh"
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.CLKA(CLK2), .CLKB(CLK3),
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.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
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.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
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.RSTA(1'b0), .RSTB(1'b0)
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);
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end else if (CFG_DBITS == 2) begin
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DP16KD #(
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`include "bram_init_1_2_4.vh"
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.DATA_WIDTH_A(2),
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.DATA_WIDTH_B(2),
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.CLKAMUX(CLKAMUX),
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.CLKBMUX(CLKBMUX),
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.WRITEMODE_A(WRITEMODE_A),
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.WRITEMODE_B("READBEFOREWRITE"),
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.GSR("DISABLED")
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) _TECHMAP_REPLACE_ (
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`include "bram_conn_2.vh"
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.CLKA(CLK2), .CLKB(CLK3),
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.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
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.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
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.RSTA(1'b0), .RSTB(1'b0)
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);
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end else if (CFG_DBITS <= 4) begin
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DP16KD #(
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`include "bram_init_1_2_4.vh"
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.DATA_WIDTH_A(4),
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.DATA_WIDTH_B(4),
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.CLKAMUX(CLKAMUX),
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.CLKBMUX(CLKBMUX),
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.WRITEMODE_A(WRITEMODE_A),
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.WRITEMODE_B("READBEFOREWRITE"),
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.GSR("DISABLED")
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) _TECHMAP_REPLACE_ (
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`include "bram_conn_4.vh"
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.CLKA(CLK2), .CLKB(CLK3),
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.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
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.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
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.RSTA(1'b0), .RSTB(1'b0)
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);
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end else if (CFG_DBITS <= 9) begin
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DP16KD #(
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`include "bram_init_9_18_36.vh"
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.DATA_WIDTH_A(9),
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.DATA_WIDTH_B(9),
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.CLKAMUX(CLKAMUX),
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.CLKBMUX(CLKBMUX),
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.WRITEMODE_A(WRITEMODE_A),
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.WRITEMODE_B("READBEFOREWRITE"),
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.GSR("DISABLED")
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) _TECHMAP_REPLACE_ (
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`include "bram_conn_9.vh"
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.CLKA(CLK2), .CLKB(CLK3),
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.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
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.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
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.RSTA(1'b0), .RSTB(1'b0)
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);
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end else if (CFG_DBITS <= 18) begin
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DP16KD #(
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`include "bram_init_9_18_36.vh"
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.DATA_WIDTH_A(18),
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.DATA_WIDTH_B(18),
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.CLKAMUX(CLKAMUX),
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.CLKBMUX(CLKBMUX),
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.WRITEMODE_A(WRITEMODE_A),
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.WRITEMODE_B("READBEFOREWRITE"),
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.GSR("DISABLED")
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) _TECHMAP_REPLACE_ (
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`include "bram_conn_18.vh"
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.CLKA(CLK2), .CLKB(CLK3),
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.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
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.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
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.RSTA(1'b0), .RSTB(1'b0)
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);
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end else begin
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wire TECHMAP_FAIL = 1'b1;
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end endgenerate
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endmodule
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