yosys/passes
Miodrag Milanovic 75032a565d Set init state for all wires from FST and set past 2022-04-22 11:57:39 +02:00
..
cmds show: Fix width labels. 2022-04-04 22:48:09 +02:00
equiv Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
fsm Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
hierarchy Reorder steps in -auto-top to fix synth command, fixes #3261 2022-04-05 14:02:37 +02:00
memory memory_share: Fix up mismatched address widths. 2022-04-15 22:01:00 +02:00
opt opt_dff: Fix behavior on $ff with D == Q. 2022-04-15 22:00:32 +02:00
pmgen Update comment 2022-02-02 03:21:09 +01:00
proc proc_dff: Emit $aldff. 2021-10-27 14:14:24 +02:00
sat Set init state for all wires from FST and set past 2022-04-22 11:57:39 +02:00
techmap abc: Add support for FFs with reset in -dff 2022-04-07 15:05:02 +02:00
tests Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00