mirror of https://github.com/YosysHQ/yosys.git
21 lines
345 B
Verilog
21 lines
345 B
Verilog
module test001(output [63:0] y);
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function [7:0] mylog2;
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input [31:0] value;
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begin
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mylog2 = 0;
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while (value > 0) begin
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value = value >> 1;
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mylog2 = mylog2 + 1;
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end
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end
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endfunction
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genvar i;
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generate
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for (i = 0; i < 64; i = i+1) begin
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localparam tmp = mylog2(i);
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assign y[i] = tmp;
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end
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endgenerate
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endmodule
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