yosys/docs/source/using_yosys/synthesis
Krystine Sherwin 3a153f99db
Add cell_libs.rst
Updates code examples, removing `counter_outputs.ys` in favour of a single script.  Also adds a .gitignore for the output file `synth.v`.
`example_synth.rst` still pending updated example.
2023-12-14 10:08:46 +13:00
..
abc.rst Updated ABC info 2023-12-13 10:08:45 +13:00
cell_libs.rst Add cell_libs.rst 2023-12-14 10:08:46 +13:00
fsm.rst Removing typical phases doc 2023-12-07 17:14:21 +13:00
index.rst Add cell_libs.rst 2023-12-14 10:08:46 +13:00
memory.rst TODOs 2023-12-12 12:05:45 +13:00
opt.rst TODOs 2023-12-12 12:05:45 +13:00
proc.rst Removing typical phases doc 2023-12-07 17:14:21 +13:00
synth.rst TODOs 2023-12-12 12:05:45 +13:00