mirror of https://github.com/YosysHQ/yosys.git
551 lines
19 KiB
C++
551 lines
19 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 Alberto Gonzalez <boqwxp@airmail.cc>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include "kernel/rtlil.h"
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#include "kernel/register.h"
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#include <cstdio>
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#include <algorithm>
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#if defined(_WIN32)
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# define WIFEXITED(x) 1
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# define WIFSIGNALED(x) 0
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# define WIFSTOPPED(x) 0
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# define WEXITSTATUS(x) ((x) & 0xff)
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# define WTERMSIG(x) SIGTERM
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#else
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# include <sys/wait.h>
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#endif
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct QbfSolutionType {
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std::vector<std::string> stdout;
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dict<std::string, std::string> hole_to_value;
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bool sat;
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bool unknown; //true if neither 'sat' nor 'unsat'
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bool success; //true if exit code 0
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QbfSolutionType() : sat(false), unknown(true), success(false) {}
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};
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struct QbfSolveOptions {
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bool specialize, specialize_from_file, write_solution, nocleanup, dump_final_smt2, assume_outputs;
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bool sat, unsat, show_smtbmc;
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std::string specialize_soln_file;
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std::string write_soln_soln_file;
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std::string dump_final_smt2_file;
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size_t argidx;
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QbfSolveOptions() : specialize(false), specialize_from_file(false), write_solution(false),
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nocleanup(false), dump_final_smt2(false), assume_outputs(false), sat(false), unsat(false),
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show_smtbmc(false), argidx(0) {};
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};
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void recover_solution(QbfSolutionType &sol) {
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YS_REGEX_TYPE sat_regex = YS_REGEX_COMPILE("Status: PASSED");
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YS_REGEX_TYPE unsat_regex = YS_REGEX_COMPILE("Solver Error.*model is not available");
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YS_REGEX_TYPE hole_value_regex = YS_REGEX_COMPILE_WITH_SUBS("Value for anyconst in [a-zA-Z0-9_]* \\(([^:]*:[^\\)]*)\\): (.*)");
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#ifndef NDEBUG
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YS_REGEX_TYPE hole_loc_regex = YS_REGEX_COMPILE("[^:]*:[0-9]+.[0-9]+-[0-9]+.[0-9]+");
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YS_REGEX_TYPE hole_val_regex = YS_REGEX_COMPILE("[0-9]+");
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#endif
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YS_REGEX_MATCH_TYPE m;
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bool sat_regex_found = false;
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bool unsat_regex_found = false;
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dict<std::string, bool> hole_value_recovered;
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for (const std::string &x : sol.stdout) {
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if(YS_REGEX_NS::regex_search(x, m, hole_value_regex)) {
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std::string loc = m[1].str();
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std::string val = m[2].str();
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#ifndef NDEBUG
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log_assert(YS_REGEX_NS::regex_search(loc, hole_loc_regex));
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log_assert(YS_REGEX_NS::regex_search(val, hole_val_regex));
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#endif
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sol.hole_to_value[loc] = val;
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}
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else if (YS_REGEX_NS::regex_search(x, sat_regex))
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sat_regex_found = true;
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else if (YS_REGEX_NS::regex_search(x, unsat_regex))
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unsat_regex_found = true;
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}
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#ifndef NDEBUG
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log_assert(!sol.unknown && sol.sat? sat_regex_found : true);
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log_assert(!sol.unknown && !sol.sat? unsat_regex_found : true);
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#endif
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}
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dict<std::string, std::string> get_hole_loc_name_map(RTLIL::Module *module, const QbfSolutionType &sol) {
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dict<std::string, std::string> hole_loc_to_name;
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for (auto cell : module->cells()) {
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std::string cell_src = cell->get_src_attribute();
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auto pos = sol.hole_to_value.find(cell_src);
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if (pos != sol.hole_to_value.end()) {
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#ifndef NDEBUG
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log_assert(cell->type.in("$anyconst", "$anyseq"));
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log_assert(cell->getPort(ID::Y).is_wire());
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#endif
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hole_loc_to_name[pos->first] = cell->getPort(ID::Y).as_wire()->name.str();
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}
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}
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return hole_loc_to_name;
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}
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void write_solution(RTLIL::Module *module, const QbfSolutionType &sol, const std::string &file) {
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std::ofstream fout(file.c_str());
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if (!fout)
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log_cmd_error("could not open solution file for writing.\n");
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dict<std::string, std::string> hole_loc_to_name = get_hole_loc_name_map(module, sol);
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for(auto &x : sol.hole_to_value)
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fout << hole_loc_to_name[x.first] << "=" << x.second << std::endl;
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}
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void specialize_from_file(RTLIL::Module *module, const std::string &file) {
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YS_REGEX_TYPE hole_assn_regex = YS_REGEX_COMPILE_WITH_SUBS("^(.*)=([01]+)$");
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YS_REGEX_MATCH_TYPE m;
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std::set<RTLIL::Cell *> anyconsts_to_remove;
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dict<std::string, std::string> hole_name_to_value;
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std::ifstream fin(file.c_str());
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if (!fin)
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log_cmd_error("could not read solution file.\n");
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std::string buf;
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while (std::getline(fin, buf)) {
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log_assert(YS_REGEX_NS::regex_search(buf, m, hole_assn_regex));
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std::string hole_name = m[1].str();
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std::string hole_value = m[2].str();
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hole_name_to_value[hole_name] = hole_value;
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}
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for (auto cell : module->cells())
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if (cell->type == "$anyconst") {
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auto anyconst_port_y = cell->getPort(ID::Y).as_wire();
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if (anyconst_port_y == nullptr)
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continue;
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if (hole_name_to_value.find(anyconst_port_y->name.str()) != hole_name_to_value.end())
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anyconsts_to_remove.insert(cell);
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}
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for (auto cell : anyconsts_to_remove)
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module->remove(cell);
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for (auto &it : hole_name_to_value) {
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std::string hole_name = it.first;
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std::string hole_value = it.second;
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RTLIL::Wire *wire = module->wire(hole_name);
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#ifndef NDEBUG
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log_assert(wire != nullptr);
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log_assert(wire->width > 0 && GetSize(hole_value) == wire->width);
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#endif
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log("Specializing %s from file with %s = %d'b%s.\n", module->name.c_str(), hole_name.c_str(), wire->width, hole_value.c_str());
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std::vector<RTLIL::SigBit> value_bv;
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value_bv.reserve(wire->width);
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for (char c : hole_value)
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value_bv.emplace_back(c == '1'? RTLIL::S1 : RTLIL::S0);
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std::reverse(value_bv.begin(), value_bv.end());
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module->connect(wire, value_bv);
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}
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}
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void specialize(RTLIL::Module *module, const QbfSolutionType &sol) {
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dict<std::string, std::string> hole_loc_to_name = get_hole_loc_name_map(module, sol);
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std::set<RTLIL::Cell *> anyconsts_to_remove;
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for (auto cell : module->cells())
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if (cell->type == "$anyconst")
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if (hole_loc_to_name.find(cell->get_src_attribute()) != hole_loc_to_name.end())
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anyconsts_to_remove.insert(cell);
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for (auto cell : anyconsts_to_remove)
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module->remove(cell);
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for (auto &it : sol.hole_to_value) {
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std::string hole_loc = it.first;
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std::string hole_value = it.second;
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#ifndef NDEBUG
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auto pos = hole_loc_to_name.find(hole_loc);
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log_assert(pos != hole_loc_to_name.end());
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#endif
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std::string hole_name = hole_loc_to_name[hole_loc];
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RTLIL::Wire *wire = module->wire(hole_name);
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#ifndef NDEBUG
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log_assert(wire != nullptr);
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log_assert(wire->width > 0 && GetSize(hole_value) == wire->width);
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#endif
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log("Specializing %s with %s = %d'b%s.\n", module->name.c_str(), hole_name.c_str(), wire->width, hole_value.c_str());
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std::vector<RTLIL::SigBit> value_bv;
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value_bv.reserve(wire->width);
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for (char c : hole_value)
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value_bv.emplace_back(c == '1'? RTLIL::S1 : RTLIL::S0);
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std::reverse(value_bv.begin(), value_bv.end());
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module->connect(wire, value_bv);
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}
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}
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void dump_model(RTLIL::Module *module, const QbfSolutionType &sol) {
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log("Satisfiable model:\n");
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dict<std::string, std::string> hole_loc_to_name = get_hole_loc_name_map(module, sol);
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for (auto &it : sol.hole_to_value) {
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std::string hole_loc = it.first;
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std::string hole_value = it.second;
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#ifndef NDEBUG
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auto pos = hole_loc_to_name.find(hole_loc);
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log_assert(pos != hole_loc_to_name.end());
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#endif
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std::string hole_name = hole_loc_to_name[hole_loc];
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log("\t%s = %lu'b%s\n", hole_name.c_str(), hole_value.size(), hole_value.c_str());
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std::vector<RTLIL::SigBit> value_bv;
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value_bv.reserve(hole_value.size());
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for (char c : hole_value)
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value_bv.emplace_back(c == '1'? RTLIL::S1 : RTLIL::S0);
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std::reverse(value_bv.begin(), value_bv.end());
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}
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}
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void allconstify_inputs(RTLIL::Module *module, const std::set<std::string> &input_wires) {
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for (auto &n : input_wires) {
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RTLIL::Wire *input = module->wire(n);
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#ifndef NDEBUG
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log_assert(input != nullptr);
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#endif
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RTLIL::Cell *allconst = module->addCell("$allconst$" + n, "$allconst");
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allconst->setParam(ID(WIDTH), input->width);
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allconst->setPort(ID::Y, input);
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allconst->set_src_attribute(input->get_src_attribute());
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input->port_input = false;
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log("Replaced input %s with $allconst cell.\n", n.c_str());
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}
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module->fixup_ports();
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}
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void assume_miter_outputs(RTLIL::Module *module) {
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std::vector<RTLIL::Wire *> wires_to_assume;
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for (auto w : module->wires())
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if (w->port_output && w->width == 1)
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wires_to_assume.push_back(w);
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if (wires_to_assume.size() == 0)
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return;
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else {
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log("Adding $assume cell for output(s): ");
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for (auto w : wires_to_assume)
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log("\"%s\" ", w->name.c_str());
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log("\n");
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}
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for(auto i = 0; wires_to_assume.size() > 1; ++i) {
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std::vector<RTLIL::Wire *> buf;
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for (auto j = 0; j + 1 < GetSize(wires_to_assume); j += 2) {
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std::stringstream strstr; strstr << i << "_" << j;
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RTLIL::Wire *and_wire = module->addWire("\\_qbfsat_and_" + strstr.str(), 1);
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module->addLogicAnd("$_qbfsat_and_" + strstr.str(), wires_to_assume[j], wires_to_assume[j+1], and_wire, false, wires_to_assume[j]->get_src_attribute());
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buf.push_back(and_wire);
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}
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if (wires_to_assume.size() % 2 == 1)
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buf.push_back(wires_to_assume[wires_to_assume.size() - 1]);
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wires_to_assume.swap(buf);
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}
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#ifndef NDEBUG
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log_assert(wires_to_assume.size() == 1);
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#endif
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module->addAssume("$assume_qbfsat_miter_outputs", wires_to_assume[0], RTLIL::S1);
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}
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QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
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QbfSolutionType ret;
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const std::string yosys_smtbmc_exe = proc_self_dirname() + "yosys-smtbmc";
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const std::string smtbmc_warning = "z3: WARNING:";
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const bool show_smtbmc = opt.show_smtbmc;
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const std::string tempdir_name = make_temp_dir("/tmp/yosys-z3-XXXXXX");
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const std::string smt2_command = "write_smt2 -stbv -wires " + tempdir_name + "/problem.smt2";
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#ifndef NDEBUG
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log_assert(mod->design != nullptr);
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#endif
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Pass::call(mod->design, smt2_command);
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log_header(mod->design, "Solving QBF-SAT problem.\n");
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//Execute and capture stdout from `yosys-smtbmc -s z3 -t 1 -g --binary [--dump-smt2 <file>]`
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{
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const std::string cmd = yosys_smtbmc_exe + " -s z3 -t 1 -g --binary " + (opt.dump_final_smt2? "--dump-smt2 " + opt.dump_final_smt2_file + " " : "") + tempdir_name + "/problem.smt2 2>&1";
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auto process_line = [&ret, &smtbmc_warning, &show_smtbmc](const std::string &line) {
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ret.stdout.push_back(line.substr(0, line.size()-1)); //don't include trailing newline
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auto warning_pos = line.find(smtbmc_warning);
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if (warning_pos != std::string::npos)
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log_warning("%s", line.substr(warning_pos + smtbmc_warning.size() + 1).c_str());
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else
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if (show_smtbmc)
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log("smtbmc output: %s", line.c_str());
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};
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log("Launching \"%s\".\n", cmd.c_str());
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int retval = run_command(cmd, process_line);
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if (retval == 0) {
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ret.sat = true;
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ret.unknown = false;
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} else if (retval == 1) {
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ret.sat = false;
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ret.unknown = false;
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}
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}
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if(!opt.nocleanup)
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remove_directory(tempdir_name);
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recover_solution(ret);
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return ret;
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}
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std::set<std::string> validate_design_and_get_inputs(RTLIL::Module *module, const QbfSolveOptions &opt) {
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bool found_input = false;
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bool found_hole = false;
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bool found_1bit_output = false;
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bool found_assert_assume = false;
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std::set<std::string> input_wires;
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for (auto wire : module->wires()) {
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if (wire->port_input) {
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found_input = true;
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input_wires.insert(wire->name.str());
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}
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if (wire->port_output && wire->width == 1)
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found_1bit_output = true;
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}
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for (auto cell : module->cells()) {
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if (cell->type == "$allconst")
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found_input = true;
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if (cell->type == "$anyconst")
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found_hole = true;
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if (cell->type.in("$assert", "$assume"))
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found_assert_assume = true;
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}
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if (!found_input)
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log_cmd_error("Can't perform QBF-SAT on a miter with no inputs!\n");
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if (!found_hole)
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log_cmd_error("Did not find any existentially-quantified variables. Use 'sat' instead.\n");
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if (!found_1bit_output && !found_assert_assume)
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log_cmd_error("Did not find any single-bit outputs or $assert/$assume cells. Is this a miter circuit?\n");
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if (!found_assert_assume && !opt.assume_outputs)
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log_cmd_error("Did not find any $assert/$assume cells. Single-bit outputs were found, but `-assume-outputs` was not specified.\n");
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return input_wires;
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}
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QbfSolveOptions parse_args(const std::vector<std::string> &args) {
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QbfSolveOptions opt;
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for (opt.argidx = 1; opt.argidx < args.size(); opt.argidx++) {
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if (args[opt.argidx] == "-nocleanup") {
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opt.nocleanup = true;
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continue;
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}
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else if (args[opt.argidx] == "-specialize") {
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opt.specialize = true;
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continue;
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}
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else if (args[opt.argidx] == "-assume-outputs") {
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opt.assume_outputs = true;
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continue;
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}
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else if (args[opt.argidx] == "-sat") {
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opt.sat = true;
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continue;
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}
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else if (args[opt.argidx] == "-unsat") {
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opt.unsat = true;
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continue;
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}
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else if (args[opt.argidx] == "-show-smtbmc") {
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opt.show_smtbmc = true;
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continue;
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}
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else if (args[opt.argidx] == "-dump-final-smt2") {
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opt.dump_final_smt2 = true;
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if (args.size() <= opt.argidx + 1)
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log_cmd_error("smt2 file not specified.\n");
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else
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opt.dump_final_smt2_file = args[++opt.argidx];
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continue;
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}
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else if (args[opt.argidx] == "-specialize-from-file") {
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opt.specialize_from_file = true;
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if (args.size() <= opt.argidx + 1)
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log_cmd_error("solution file not specified.\n");
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else
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opt.specialize_soln_file = args[++opt.argidx];
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continue;
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}
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else if (args[opt.argidx] == "-write-solution") {
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opt.write_solution = true;
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if (args.size() <= opt.argidx + 1)
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log_cmd_error("solution file not specified.\n");
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else
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opt.write_soln_soln_file = args[++opt.argidx];
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continue;
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}
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break;
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}
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return opt;
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}
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void print_proof_failed()
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{
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log("\n");
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log(" ______ ___ ___ _ _ _ _ \n");
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log(" (_____ \\ / __) / __) (_) | | | |\n");
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log(" _____) )___ ___ ___ _| |__ _| |__ _____ _| | _____ __| | |\n");
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log(" | ____/ ___) _ \\ / _ (_ __) (_ __|____ | | || ___ |/ _ |_|\n");
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log(" | | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_ \n");
|
|
log(" |_| |_| \\___/ \\___/ |_| |_| \\_____|_|\\_)_____)\\____|_|\n");
|
|
log("\n");
|
|
}
|
|
|
|
void print_qed()
|
|
{
|
|
log("\n");
|
|
log(" /$$$$$$ /$$$$$$$$ /$$$$$$$ \n");
|
|
log(" /$$__ $$ | $$_____/ | $$__ $$ \n");
|
|
log(" | $$ \\ $$ | $$ | $$ \\ $$ \n");
|
|
log(" | $$ | $$ | $$$$$ | $$ | $$ \n");
|
|
log(" | $$ | $$ | $$__/ | $$ | $$ \n");
|
|
log(" | $$/$$ $$ | $$ | $$ | $$ \n");
|
|
log(" | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$\n");
|
|
log(" \\____ $$$|__/|________/|__/|_______/|__/\n");
|
|
log(" \\__/ \n");
|
|
log("\n");
|
|
}
|
|
|
|
struct QbfSatPass : public Pass {
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|
QbfSatPass() : Pass("qbfsat", "solve a 2QBF-SAT problem in the circuit") { }
|
|
void help() YS_OVERRIDE
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" qbfsat [options] [selection]\n");
|
|
log("\n");
|
|
log("This command solves a 2QBF-SAT problem defined over the currently selected module.\n");
|
|
log("Existentially-quantified variables are declared by assigning a wire \"$anyconst\".\n");
|
|
log("Universally-quantified variables may be explicitly declared by assigning a wire\n");
|
|
log("\"$allconst\", but module inputs will be treated as universally-quantified variables\n");
|
|
log("by default.\n");
|
|
log("\n");
|
|
log(" -nocleanup\n");
|
|
log(" Do not delete temporary files and directories. Useful for\n");
|
|
log(" debugging.\n");
|
|
log("\n");
|
|
log(" -dump-final-smt2 <file>\n");
|
|
log(" Pass the --dump-smt2 option to yosys-smtbmc.\n");
|
|
log("\n");
|
|
log(" -assume-outputs\n");
|
|
log(" Add an $assume cell for the conjunction of all one-bit module output wires.\n");
|
|
log("\n");
|
|
log(" -sat\n");
|
|
log(" Generate an error if the solver does not return \"sat\".\n");
|
|
log("\n");
|
|
log(" -unsat\n");
|
|
log(" Generate an error if the solver does not return \"unsat\".\n");
|
|
log("\n");
|
|
log(" -show-smtbmc\n");
|
|
log(" Print the output from yosys-smtbmc.\n");
|
|
log("\n");
|
|
log(" -specialize\n");
|
|
log(" Replace all \"$anyconst\" cells with constant values determined by the solver.\n");
|
|
log("\n");
|
|
log(" -specialize-from-file <solution file>\n");
|
|
log(" Do not run the solver, but instead only attempt to replace all \"$anyconst\"\n");
|
|
log(" cells in the current module with values provided by the specified file.\n");
|
|
log("\n");
|
|
log(" -write-solution <solution file>\n");
|
|
log(" Write the assignments discovered by the solver for all \"$anyconst\" cells\n");
|
|
log(" to the specified file.");
|
|
log("\n");
|
|
log("\n");
|
|
}
|
|
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
|
{
|
|
log_header(design, "Executing QBFSAT pass (solving QBF-SAT problems in the circuit).\n");
|
|
QbfSolveOptions opt = parse_args(args);
|
|
extra_args(args, opt.argidx, design);
|
|
|
|
RTLIL::Module *module = nullptr;
|
|
for (auto mod : design->selected_modules()) {
|
|
if (module)
|
|
log_cmd_error("Only one module must be selected for the QBF-SAT pass! (selected: %s and %s)\n", log_id(module), log_id(mod));
|
|
module = mod;
|
|
}
|
|
if (module == nullptr)
|
|
log_cmd_error("Can't perform QBF-SAT on an empty selection!\n");
|
|
|
|
log_push();
|
|
if (!opt.specialize_from_file) {
|
|
//Save the design to restore after modiyfing the current module.
|
|
std::string module_name = module->name.str();
|
|
Pass::call(design, "design -push-copy");
|
|
|
|
//Replace input wires with wires assigned $allconst cells.
|
|
std::set<std::string> input_wires = validate_design_and_get_inputs(module, opt);
|
|
allconstify_inputs(module, input_wires);
|
|
if (opt.assume_outputs)
|
|
assume_miter_outputs(module);
|
|
|
|
QbfSolutionType ret = qbf_solve(module, opt);
|
|
Pass::call(design, "design -pop");
|
|
module = design->module(module_name);
|
|
|
|
if (ret.unknown)
|
|
log_warning("solver did not give an answer\n");
|
|
else if (ret.sat)
|
|
print_qed();
|
|
else
|
|
print_proof_failed();
|
|
|
|
if(!ret.unknown && ret.sat) {
|
|
if (opt.write_solution) {
|
|
write_solution(module, ret, opt.write_soln_soln_file);
|
|
}
|
|
if (opt.specialize) {
|
|
specialize(module, ret);
|
|
} else {
|
|
dump_model(module, ret);
|
|
}
|
|
if (opt.unsat)
|
|
log_cmd_error("expected problem to be UNSAT\n");
|
|
}
|
|
else if (!ret.unknown && !ret.sat && opt.sat)
|
|
log_cmd_error("expected problem to be SAT\n");
|
|
else if (ret.unknown && (opt.sat || opt.unsat))
|
|
log_cmd_error("expected problem to be %s\n", opt.sat? "SAT" : "UNSAT");
|
|
} else
|
|
specialize_from_file(module, opt.specialize_soln_file);
|
|
log_pop();
|
|
}
|
|
} QbfSatPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|