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yosys/techlibs/gowin
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Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 		2021-06-08 00:39:36 +02:00
..
.gitignore gowin: Add missing .gitignore entries 2019-11-22 14:40:36 +01:00
Makefile.inc gowin: replace determine_init with setundef 2020-07-04 23:26:56 +02:00
arith_map.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
brams.txt Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
brams_init.py support bram initialisation 2019-09-05 17:25:51 +02:00
brams_init3.vh GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow 2019-04-12 23:40:02 -05:00
brams_map.v add 32-bit BRAM and byte-enables 2019-10-28 10:33:27 +01:00
cells_map.v gowin: Use dfflegalize. 2020-07-06 12:27:46 +02:00
cells_sim.v synth_gowin: Add rPLL blackbox 2020-11-11 17:06:54 +01:00
lutrams.txt Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
lutrams_map.v Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
synth_gowin.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00