mirror of https://github.com/YosysHQ/yosys.git
253 lines
12 KiB
Verilog
253 lines
12 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module \$__SHREG_ (input C, input D, input E, output Q);
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parameter DEPTH = 0;
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parameter [DEPTH-1:0] INIT = 0;
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parameter CLKPOL = 1;
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parameter ENPOL = 2;
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\$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q));
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endmodule
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module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
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parameter DEPTH = 0;
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parameter [DEPTH-1:0] INIT = 0;
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parameter CLKPOL = 1;
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parameter ENPOL = 2;
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// shregmap's INIT parameter shifts out LSB first;
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// however Xilinx expects MSB first
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function [DEPTH-1:0] brev;
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input [DEPTH-1:0] din;
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integer i;
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begin
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for (i = 0; i < DEPTH; i=i+1)
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brev[i] = din[DEPTH-1-i];
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end
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endfunction
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localparam [DEPTH-1:0] INIT_R = brev(INIT);
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parameter _TECHMAP_CONSTMSK_L_ = 0;
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parameter _TECHMAP_CONSTVAL_L_ = 0;
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wire CE;
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generate
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if (ENPOL == 0)
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assign CE = ~E;
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else if (ENPOL == 1)
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assign CE = E;
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else
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assign CE = 1'b1;
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if (DEPTH == 1) begin
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if (CLKPOL)
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FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
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else
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FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
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end else
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if (DEPTH <= 16) begin
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SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));
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end else
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if (DEPTH > 17 && DEPTH <= 32) begin
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SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));
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end else
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if (DEPTH > 33 && DEPTH <= 64) begin
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wire T0, T1, T2;
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SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
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\$__XILINX_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));
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if (&_TECHMAP_CONSTMSK_L_)
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assign Q = T2;
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else
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MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));
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end else
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if (DEPTH > 65 && DEPTH <= 96) begin
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wire T0, T1, T2, T3, T4, T5, T6;
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SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
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SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
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\$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
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if (&_TECHMAP_CONSTMSK_L_)
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assign Q = T4;
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else begin
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MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(L[5]));
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MUXF7 fpga_mux_1 (.O(T6), .I0(T4), .I1(1'b0 /* unused */), .S(L[5]));
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MUXF8 fpga_mux_2 (.O(Q), .I0(T5), .I1(T6), .S(L[6]));
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end
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end else
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if (DEPTH > 97 && DEPTH < 128) begin
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wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
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SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
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SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
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SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
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\$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
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if (&_TECHMAP_CONSTMSK_L_)
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assign Q = T6;
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else begin
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MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(L[5]));
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MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(L[5]));
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MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
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end
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end
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else if (DEPTH == 128) begin
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wire T0, T1, T2, T3, T4, T5, T6;
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SRLC32E #(.INIT(INIT_R[ 32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
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SRLC32E #(.INIT(INIT_R[ 64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
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SRLC32E #(.INIT(INIT_R[ 96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
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SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO));
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if (&_TECHMAP_CONSTMSK_L_)
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assign Q = T6;
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else begin
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wire T7, T8;
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MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(L[5]));
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MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(L[5]));
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MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
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end
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end
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else if (DEPTH <= 129 && ~&_TECHMAP_CONSTMSK_L_) begin
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// Handle cases where fixed-length depth is
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// just 1 over a convenient value
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\$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
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end
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else begin
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localparam lower_clog2 = $clog2((DEPTH+1)/2);
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localparam lower_depth = 2 ** lower_clog2;
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wire T0, T1, T2, T3;
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if (&_TECHMAP_CONSTMSK_L_) begin
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\$__XILINX_SHREG_ #(.DEPTH(lower_depth), .INIT(INIT[DEPTH-1:DEPTH-lower_depth]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(lower_depth-1), .E(E), .Q(T0));
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\$__XILINX_SHREG_ #(.DEPTH(DEPTH-lower_depth), .INIT(INIT[DEPTH-lower_depth-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .L(DEPTH-lower_depth-1), .E(E), .Q(Q), .SO(T3));
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end
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else begin
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\$__XILINX_SHREG_ #(.DEPTH(lower_depth), .INIT(INIT[DEPTH-1:DEPTH-lower_depth]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(L[lower_clog2-1:0]), .E(E), .Q(T0), .SO(T1));
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\$__XILINX_SHREG_ #(.DEPTH(DEPTH-lower_depth), .INIT(INIT[DEPTH-lower_depth-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L[lower_clog2-1:0]), .E(E), .Q(T2), .SO(T3));
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assign Q = L[lower_clog2] ? T2 : T0;
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end
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if (DEPTH == 2 * lower_depth)
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assign SO = T3;
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end
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endgenerate
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endmodule
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module \$__XILINX_MUX_ (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
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parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
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function integer compute_num_leading_X_in_A;
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integer i, c;
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begin
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compute_num_leading_X_in_A = 0;
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c = 1;
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for (i = A_WIDTH-1; i >= 0; i=i-1) begin
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if (!_TECHMAP_CONSTMSK_A_[i] || _TECHMAP_CONSTVAL_A_[i] !== 1'bx)
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c = 0;
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compute_num_leading_X_in_A = compute_num_leading_X_in_A + c;
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end
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end
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endfunction
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localparam num_leading_X_in_A = compute_num_leading_X_in_A();
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generate
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genvar i, j;
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// Bit-blast
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if (Y_WIDTH > 1) begin
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for (i = 0; i < Y_WIDTH; i++)
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\$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
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end
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// If the LSB of B is constant zero (and Y_WIDTH is 1) then
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// we can optimise by removing every other entry from A
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// and popping the constant zero from B
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else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
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wire [(A_WIDTH+1)/2-1:0] A_i;
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for (i = 0; i < (A_WIDTH+1)/2; i++)
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assign A_i[i] = A[i*2];
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\$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
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end
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// Trim off any leading 1'bx -es in A, and resize B accordingly
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else if (num_leading_X_in_A > 0) begin
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localparam A_WIDTH_new = A_WIDTH - num_leading_X_in_A;
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localparam B_WIDTH_new = $clog2(A_WIDTH_new);
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\$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y));
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end
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else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
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end
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else if (B_WIDTH == 3) begin
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localparam a_width0 = 2 ** 2;
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localparam a_widthN = A_WIDTH - a_width0;
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wire T0, T1;
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[a_width0-1:0]), .B(B[2-1:0]), .Y(T0));
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if (a_widthN > 1)
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
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else
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assign T1 = A[A_WIDTH-1];
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MUXF7 fpga_hard_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
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end
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else if (B_WIDTH == 4) begin
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localparam a_width0 = 2 ** 2;
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localparam num_mux8 = A_WIDTH / a_width0;
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localparam a_widthN = A_WIDTH - num_mux8*a_width0;
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wire [4-1:0] T;
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wire T0, T1;
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for (i = 0; i < 4; i++)
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if (i < num_mux8)
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i]));
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else if (i == num_mux8 && a_widthN > 0) begin
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if (a_widthN > 1)
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
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else
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assign T[i] = A[A_WIDTH-1];
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end
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else
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assign T[i] = 1'bx;
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MUXF7 fpga_hard_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0));
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MUXF7 fpga_hard_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1));
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MUXF8 fpga_hard_mux_2 (.I0(T0), .I1(T1), .S(B[3]), .O(Y));
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end
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else begin
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localparam a_width0 = 2 ** 4;
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localparam num_mux16 = A_WIDTH / a_width0;
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localparam a_widthN = A_WIDTH - num_mux16*a_width0;
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wire [(2**(B_WIDTH-4))-1:0] T;
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for (i = 0; i < 2 ** (B_WIDTH-4); i++)
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if (i < num_mux16)
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\$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
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else if (i == num_mux16 && a_widthN > 0) begin
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if (a_widthN > 1)
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\$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
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else
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assign T[i] = A[A_WIDTH-1];
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end
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else
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assign T[i] = 1'bx;
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\$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
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end
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endgenerate
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endmodule
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