mirror of https://github.com/YosysHQ/yosys.git
64 lines
1.1 KiB
Plaintext
64 lines
1.1 KiB
Plaintext
read_verilog <<EOT
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module test(input a, output [1:0] y);
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assign y = {a,1'b0} + 1'b1;
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endmodule
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EOT
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alumacc
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equiv_opt opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-count none t:$pos t:* %D
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design -reset
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read_verilog <<EOT
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module test(input a, output [1:0] y);
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assign y = {a,1'b1} + 1'b1;
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endmodule
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EOT
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alumacc
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select -assert-count 1 t:$alu
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select -assert-count none t:$alu t:* %D
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design -reset
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read_verilog <<EOT
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module test(input a, output [1:0] y);
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assign y = {a,1'b1} - 1'b1;
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endmodule
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EOT
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equiv_opt opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-count none t:$pos t:* %D
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design -reset
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read_verilog <<EOT
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module test(input a, output [3:0] y);
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assign y = {a,3'b101} - 1'b1;
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endmodule
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EOT
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equiv_opt opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-count none t:$pos t:* %D
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design -reset
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read_verilog <<EOT
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module test(input a, output [3:0] y);
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assign y = {a,3'b101} - 1'b1;
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endmodule
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EOT
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alumacc
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equiv_opt opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-count none t:$pos t:* %D
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