mirror of https://github.com/YosysHQ/yosys.git
307 lines
8.7 KiB
C++
307 lines
8.7 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <stdio.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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SigMap assign_map, dff_init_map;
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SigSet<RTLIL::Cell*> mux_drivers;
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dict<SigBit, pool<SigBit>> init_attributes;
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void remove_init_attr(SigSpec sig)
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{
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for (auto bit : assign_map(sig))
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if (init_attributes.count(bit))
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for (auto wbit : init_attributes.at(bit))
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wbit.wire->attributes.at("\\init")[wbit.offset] = State::Sx;
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}
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bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch)
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{
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SigSpec sig_e = dlatch->getPort("\\EN");
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if (sig_e == State::S0)
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{
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RTLIL::Const val_init;
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for (auto bit : dff_init_map(dlatch->getPort("\\Q")))
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val_init.bits.push_back(bit.wire == NULL ? bit.data : State::Sx);
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mod->connect(dlatch->getPort("\\Q"), val_init);
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goto delete_dlatch;
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}
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if (sig_e == State::S1)
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{
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mod->connect(dlatch->getPort("\\Q"), dlatch->getPort("\\D"));
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goto delete_dlatch;
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}
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return false;
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delete_dlatch:
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log("Removing %s (%s) from module %s.\n", log_id(dlatch), log_id(dlatch->type), log_id(mod));
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remove_init_attr(dlatch->getPort("\\Q"));
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mod->remove(dlatch);
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return true;
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}
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bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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{
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RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r;
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RTLIL::Const val_cp, val_rp, val_rv;
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if (dff->type == "$_DFF_N_" || dff->type == "$_DFF_P_") {
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sig_d = dff->getPort("\\D");
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sig_q = dff->getPort("\\Q");
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sig_c = dff->getPort("\\C");
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val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1);
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}
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else if (dff->type.substr(0,6) == "$_DFF_" && dff->type.substr(9) == "_" &&
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(dff->type[6] == 'N' || dff->type[6] == 'P') &&
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(dff->type[7] == 'N' || dff->type[7] == 'P') &&
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(dff->type[8] == '0' || dff->type[8] == '1')) {
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sig_d = dff->getPort("\\D");
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sig_q = dff->getPort("\\Q");
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sig_c = dff->getPort("\\C");
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sig_r = dff->getPort("\\R");
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val_cp = RTLIL::Const(dff->type[6] == 'P', 1);
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val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
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val_rv = RTLIL::Const(dff->type[8] == '1', 1);
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}
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else if (dff->type == "$dff") {
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sig_d = dff->getPort("\\D");
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sig_q = dff->getPort("\\Q");
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sig_c = dff->getPort("\\CLK");
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val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
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}
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else if (dff->type == "$adff") {
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sig_d = dff->getPort("\\D");
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sig_q = dff->getPort("\\Q");
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sig_c = dff->getPort("\\CLK");
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sig_r = dff->getPort("\\ARST");
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val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
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val_rp = RTLIL::Const(dff->parameters["\\ARST_POLARITY"].as_bool(), 1);
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val_rv = dff->parameters["\\ARST_VALUE"];
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}
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else
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log_abort();
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assign_map.apply(sig_d);
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assign_map.apply(sig_q);
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assign_map.apply(sig_c);
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assign_map.apply(sig_r);
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bool has_init = false;
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RTLIL::Const val_init;
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for (auto bit : dff_init_map(sig_q).to_sigbit_vector()) {
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if (bit.wire == NULL)
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has_init = true;
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val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx);
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}
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if (dff->type == "$dff" && mux_drivers.has(sig_d)) {
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std::set<RTLIL::Cell*> muxes;
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mux_drivers.find(sig_d, muxes);
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for (auto mux : muxes) {
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RTLIL::SigSpec sig_a = assign_map(mux->getPort("\\A"));
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RTLIL::SigSpec sig_b = assign_map(mux->getPort("\\B"));
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if (sig_a == sig_q && sig_b.is_fully_const() && (!has_init || val_init == sig_b.as_const())) {
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mod->connect(sig_q, sig_b);
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goto delete_dff;
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}
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if (sig_b == sig_q && sig_a.is_fully_const() && (!has_init || val_init == sig_a.as_const())) {
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mod->connect(sig_q, sig_a);
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goto delete_dff;
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}
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}
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}
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if (sig_c.is_fully_const() && (!sig_r.size() || !has_init || val_init == val_rv)) {
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if (val_rv.bits.size() == 0)
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val_rv = val_init;
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mod->connect(sig_q, val_rv);
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goto delete_dff;
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}
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if (sig_d.is_fully_undef() && sig_r.size() && (!has_init || val_init == val_rv)) {
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mod->connect(sig_q, val_rv);
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goto delete_dff;
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}
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if (sig_d.is_fully_undef() && !sig_r.size() && has_init) {
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mod->connect(sig_q, val_init);
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goto delete_dff;
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}
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if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const())) {
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mod->connect(sig_q, sig_d);
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goto delete_dff;
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}
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if (sig_d == sig_q && (!sig_r.size() || !has_init || val_init == val_rv)) {
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if (sig_r.size())
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mod->connect(sig_q, val_rv);
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if (has_init)
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mod->connect(sig_q, val_init);
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goto delete_dff;
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}
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return false;
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delete_dff:
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log("Removing %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod));
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remove_init_attr(dff->getPort("\\Q"));
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mod->remove(dff);
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return true;
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}
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struct OptRmdffPass : public Pass {
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OptRmdffPass() : Pass("opt_rmdff", "remove DFFs with constant inputs") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_rmdff [selection]\n");
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log("\n");
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log("This pass identifies flip-flops with constant inputs and replaces them with\n");
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log("a constant driver.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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int total_count = 0, total_initdrv = 0;
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log_header(design, "Executing OPT_RMDFF pass (remove dff with constant values).\n");
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extra_args(args, 1, design);
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for (auto module : design->selected_modules())
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{
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pool<SigBit> driven_bits;
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dict<SigBit, State> init_bits;
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assign_map.set(module);
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dff_init_map.set(module);
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for (auto wire : module->wires())
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{
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if (wire->attributes.count("\\init") != 0) {
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Const initval = wire->attributes.at("\\init");
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dff_init_map.add(wire, initval);
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for (int i = 0; i < GetSize(wire); i++) {
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SigBit wire_bit(wire, i), mapped_bit = assign_map(wire_bit);
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if (mapped_bit.wire) {
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init_attributes[mapped_bit].insert(wire_bit);
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if (i < GetSize(initval))
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init_bits[mapped_bit] = initval[i];
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}
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}
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}
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if (wire->port_input) {
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for (auto bit : assign_map(wire))
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driven_bits.insert(bit);
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}
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}
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mux_drivers.clear();
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std::vector<RTLIL::IdString> dff_list;
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std::vector<RTLIL::IdString> dlatch_list;
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for (auto cell : module->cells())
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{
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for (auto &conn : cell->connections())
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if (cell->output(conn.first) || !cell->known())
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for (auto bit : assign_map(conn.second))
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driven_bits.insert(bit);
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if (cell->type == "$mux" || cell->type == "$pmux") {
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if (cell->getPort("\\A").size() == cell->getPort("\\B").size())
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mux_drivers.insert(assign_map(cell->getPort("\\Y")), cell);
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continue;
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}
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if (!design->selected(module, cell))
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continue;
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if (cell->type.in("$_DFF_N_", "$_DFF_P_",
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"$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
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"$_DFF_PN0_", "$_DFF_PN1_", "$_DFF_PP0_", "$_DFF_PP1_",
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"$dff", "$adff"))
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dff_list.push_back(cell->name);
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if (cell->type == "$dlatch")
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dlatch_list.push_back(cell->name);
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}
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for (auto &id : dff_list) {
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if (module->cell(id) != nullptr &&
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handle_dff(module, module->cells_[id]))
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total_count++;
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}
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for (auto &id : dlatch_list) {
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if (module->cell(id) != nullptr &&
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handle_dlatch(module, module->cells_[id]))
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total_count++;
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}
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SigSpec const_init_sigs;
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for (auto bit : init_bits)
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if (!driven_bits.count(bit.first))
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const_init_sigs.append(bit.first);
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const_init_sigs.sort_and_unify();
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for (SigSpec sig : const_init_sigs.chunks())
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{
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Const val;
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for (auto bit : sig)
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val.bits.push_back(init_bits.at(bit));
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log("Promoting init spec %s = %s to constant driver in module %s.\n",
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log_signal(sig), log_signal(val), log_id(module));
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module->connect(sig, val);
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remove_init_attr(sig);
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total_initdrv++;
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}
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}
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assign_map.clear();
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mux_drivers.clear();
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if (total_count || total_initdrv)
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design->scratchpad_set_bool("opt.did_something", true);
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if (total_initdrv)
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log("Promoted %d init specs to constant drivers.\n", total_initdrv);
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if (total_count)
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log("Replaced %d DFF cells.\n", total_count);
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}
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} OptRmdffPass;
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PRIVATE_NAMESPACE_END
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