mirror of https://github.com/YosysHQ/yosys.git
42 lines
742 B
Verilog
42 lines
742 B
Verilog
module IBUF(input I, output O);
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assign O = I;
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endmodule
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module IOBUFE(input I, input E, output O, inout IO);
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assign O = IO;
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assign IO = E ? I : 1'bz;
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endmodule
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module ANDTERM(IN, OUT);
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parameter WIDTH = 0;
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input [(WIDTH*2)-1:0] IN;
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output reg OUT;
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integer i;
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always @(*) begin
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OUT = 1;
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for (i = 0; i < WIDTH; i=i+1) begin
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OUT = OUT & ~IN[i * 2 + 0];
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OUT = OUT & IN[i * 2 + 1];
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end
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end
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endmodule
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module ORTERM(IN, OUT);
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parameter WIDTH = 0;
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input [WIDTH-1:0] IN;
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output reg OUT;
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integer i;
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always @(*) begin
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OUT = 0;
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for (i = 0; i < WIDTH; i=i+1) begin
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OUT = OUT | IN[i];
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end
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end
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endmodule
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