mirror of https://github.com/YosysHQ/yosys.git
3174 lines
151 KiB
C++
3174 lines
151 KiB
C++
#ifdef WITH_PYTHON
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#include "yosys.h"
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#include <boost/python/module.hpp>
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#include <boost/python/class.hpp>
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#include <boost/python/wrapper.hpp>
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#include <boost/python/call.hpp>
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#include <boost/python.hpp>
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#include <boost/log/exceptions.hpp>
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using namespace Yosys;
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namespace YOSYS_PYTHON {
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struct IdString;
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struct Const;
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struct CaseRule;
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struct SwitchRule;
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struct SyncRule;
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struct Process;
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struct SigChunk;
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struct SigBit;
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struct SigSpec;
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struct Cell;
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struct Wire;
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struct Memory;
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struct Module;
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struct Design;
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struct Monitor;
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typedef Yosys::RTLIL::State State;
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void run(std::string command)
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{
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Yosys::run_pass(command);
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}
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void log(std::string text)
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{
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Yosys::log(text.c_str());
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}
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struct IdString
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{
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Yosys::RTLIL::IdString* ref_obj;
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IdString(Yosys::RTLIL::IdString* ref = new Yosys::RTLIL::IdString())
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{
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this->ref_obj = new Yosys::RTLIL::IdString(*ref);
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}
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~IdString()
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{
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delete(this->ref_obj);
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}
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IdString(Yosys::RTLIL::IdString ref)
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{
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this->ref_obj = new Yosys::RTLIL::IdString(ref);
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}
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IdString(const std::string &str)
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{
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this->ref_obj = new Yosys::RTLIL::IdString(str);
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}
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Yosys::RTLIL::IdString* get_cpp_obj() const
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{
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return ref_obj;
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}
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//WRAPPED static inline int get_reference(int idx)
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static inline int get_reference(int idx);
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//WRAPPED static inline void put_reference(int idx)
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static inline void put_reference(int idx);
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//WRAPPED bool in(IdString rhs) const { return *this == rhs; }
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bool in_IdString(IdString *rhs);
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//WRAPPED bool in(const std::string &rhs) const { return *this == rhs; }
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bool in_std_string(std::string rhs);
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};
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std::ostream &operator<<(std::ostream &ostr, const IdString &ref)
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{
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ostr << ref.ref_obj->str();
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return ostr;
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}
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struct Const
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{
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Yosys::RTLIL::Const* ref_obj;
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Const(Yosys::RTLIL::Const* ref = new Yosys::RTLIL::Const())
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{
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this->ref_obj = new Yosys::RTLIL::Const(*ref);
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}
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~Const()
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{
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delete(this->ref_obj);
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}
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Const(Yosys::RTLIL::Const ref)
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{
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this->ref_obj = new Yosys::RTLIL::Const(ref);
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}
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Yosys::RTLIL::Const* get_cpp_obj() const
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{
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return ref_obj;
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}
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//WRAPPED int as_int(bool is_signed = false) const;
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int as_int(bool is_signed = false);
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//WRAPPED static Const from_string(std::string str);
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static Const from_string(std::string str);
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//WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const {
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inline Const extract(int offset, int len = 1, State padding = RTLIL::State::S0);
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};
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std::ostream &operator<<(std::ostream &ostr, const Const &ref)
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{
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ostr << ref.ref_obj->as_string();
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return ostr;
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}
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struct CaseRule
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{
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Yosys::RTLIL::CaseRule* ref_obj;
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CaseRule(Yosys::RTLIL::CaseRule* ref = new Yosys::RTLIL::CaseRule())
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{
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this->ref_obj = ref->clone();
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}
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~CaseRule()
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{
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delete(this->ref_obj);
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}
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CaseRule(Yosys::RTLIL::CaseRule ref)
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{
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this->ref_obj = ref.clone();
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}
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Yosys::RTLIL::CaseRule* get_cpp_obj() const
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{
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return ref_obj;
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}
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};
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std::ostream &operator<<(std::ostream &ostr, const CaseRule &ref)
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{
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ostr << "CaseRule object at " << ref.ref_obj;
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return ostr;
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}
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struct SwitchRule
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{
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Yosys::RTLIL::SwitchRule* ref_obj;
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SwitchRule(Yosys::RTLIL::SwitchRule* ref = new Yosys::RTLIL::SwitchRule())
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{
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this->ref_obj = ref->clone();
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}
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~SwitchRule()
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{
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delete(this->ref_obj);
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}
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SwitchRule(Yosys::RTLIL::SwitchRule ref)
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{
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this->ref_obj = ref.clone();
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}
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Yosys::RTLIL::SwitchRule* get_cpp_obj() const
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{
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return ref_obj;
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}
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};
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std::ostream &operator<<(std::ostream &ostr, const SwitchRule &ref)
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{
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ostr << "SwitchRule object at " << ref.ref_obj;
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return ostr;
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}
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struct SyncRule
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{
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Yosys::RTLIL::SyncRule* ref_obj;
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SyncRule(Yosys::RTLIL::SyncRule* ref = new Yosys::RTLIL::SyncRule())
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{
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this->ref_obj = ref->clone();
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}
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~SyncRule()
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{
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delete(this->ref_obj);
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}
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SyncRule(Yosys::RTLIL::SyncRule ref)
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{
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this->ref_obj = ref.clone();
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}
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Yosys::RTLIL::SyncRule* get_cpp_obj() const
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{
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return ref_obj;
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}
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};
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std::ostream &operator<<(std::ostream &ostr, const SyncRule &ref)
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{
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ostr << "SyncRule object at " << ref.ref_obj;
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return ostr;
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}
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struct Process
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{
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Yosys::RTLIL::Process* ref_obj;
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Process(Yosys::RTLIL::Process* ref = new Yosys::RTLIL::Process())
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{
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this->ref_obj = ref->clone();
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}
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~Process()
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{
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delete(this->ref_obj);
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}
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Process(Yosys::RTLIL::Process ref)
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{
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this->ref_obj = ref.clone();
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}
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Yosys::RTLIL::Process* get_cpp_obj() const
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{
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return ref_obj;
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}
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};
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std::ostream &operator<<(std::ostream &ostr, const Process &ref)
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{
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ostr << "Process with name " << ref.ref_obj->name.c_str();
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return ostr;
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}
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struct SigChunk
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{
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Yosys::RTLIL::SigChunk* ref_obj;
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SigChunk(Yosys::RTLIL::SigChunk* ref = new Yosys::RTLIL::SigChunk())
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{
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this->ref_obj = new Yosys::RTLIL::SigChunk(*ref);
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}
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~SigChunk()
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{
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delete(this->ref_obj);
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}
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SigChunk(Yosys::RTLIL::SigChunk ref)
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{
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this->ref_obj = new Yosys::RTLIL::SigChunk(ref);
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}
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Yosys::RTLIL::SigChunk* get_cpp_obj() const
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{
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return ref_obj;
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}
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//WRAPPED RTLIL::SigChunk extract(int offset, int length) const;
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SigChunk extract(int offset, int length);
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};
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std::ostream &operator<<(std::ostream &ostr, const SigChunk &ref)
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{
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ostr << "SigChunk object at " << ref.ref_obj;
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return ostr;
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}
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struct SigBit
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{
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Yosys::RTLIL::SigBit* ref_obj;
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SigBit(Yosys::RTLIL::SigBit* ref = new Yosys::RTLIL::SigBit())
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{
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this->ref_obj = new Yosys::RTLIL::SigBit(*ref);
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}
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~SigBit()
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{
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delete(this->ref_obj);
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}
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SigBit(Yosys::RTLIL::SigBit ref)
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{
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this->ref_obj = new Yosys::RTLIL::SigBit(ref);
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}
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Yosys::RTLIL::SigBit* get_cpp_obj() const
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{
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return ref_obj;
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}
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};
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std::ostream &operator<<(std::ostream &ostr, const SigBit &ref)
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{
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ostr << "SigBit object at " << ref.ref_obj;
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return ostr;
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}
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struct SigSpec
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{
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Yosys::RTLIL::SigSpec* ref_obj;
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SigSpec(Yosys::RTLIL::SigSpec* ref = new Yosys::RTLIL::SigSpec())
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{
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this->ref_obj = new Yosys::RTLIL::SigSpec(*ref);
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}
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~SigSpec()
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{
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delete(this->ref_obj);
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}
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SigSpec(Yosys::RTLIL::SigSpec ref)
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{
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this->ref_obj = new Yosys::RTLIL::SigSpec(ref);
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}
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Yosys::RTLIL::SigSpec* get_cpp_obj() const
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{
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return ref_obj;
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}
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//WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);
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void replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with);
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//WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;
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void replace_SigSpec_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with, SigSpec *other);
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//WRAPPED void replace(int offset, const RTLIL::SigSpec &with);
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void replace_int_SigSpec(int offset, SigSpec *with);
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//WRAPPED void remove(const RTLIL::SigSpec &pattern);
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void remove_SigSpec(SigSpec *pattern);
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//WRAPPED void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;
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void remove_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other);
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//WRAPPED void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);
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void remove2_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other);
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//WRAPPED void remove(const pool<RTLIL::SigBit> &pattern);
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void remove_pool_SigBit(boost::python::list *pattern);
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//WRAPPED void remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;
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void remove_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other);
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//WRAPPED void remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);
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void remove2_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other);
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//WRAPPED void remove(int offset, int length = 1);
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void remove_int_int(int offset, int length = 1);
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//WRAPPED RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;
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SigSpec extract_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other);
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//WRAPPED RTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;
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SigSpec extract_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other);
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//WRAPPED RTLIL::SigSpec extract(int offset, int length = 1) const;
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SigSpec extract_int_int(int offset, int length = 1);
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//WRAPPED void append(const RTLIL::SigSpec &signal);
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void append(SigSpec *signal);
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//WRAPPED void append_bit(const RTLIL::SigBit &bit);
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void append_bit(SigBit *bit);
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//WRAPPED void extend_u0(int width, bool is_signed = false);
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void extend_u0(int width, bool is_signed = false);
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//WRAPPED RTLIL::SigSpec repeat(int num) const;
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SigSpec repeat(int num);
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//WRAPPED int as_int(bool is_signed = false) const;
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int as_int(bool is_signed = false);
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//WRAPPED bool match(std::string pattern) const;
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bool match(std::string pattern);
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//WRAPPED static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);
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static bool parse(SigSpec *sig, Module *module, std::string str);
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//WRAPPED static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);
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static bool parse_sel(SigSpec *sig, Design *design, Module *module, std::string str);
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//WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);
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static bool parse_rhs(SigSpec *lhs, SigSpec *sig, Module *module, std::string str);
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};
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std::ostream &operator<<(std::ostream &ostr, const SigSpec &ref)
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{
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ostr << "SigSpec object at " << ref.ref_obj;
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return ostr;
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}
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struct Cell
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{
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unsigned int hashidx_;
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Yosys::RTLIL::Cell* ref_obj;
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Cell(Yosys::RTLIL::Cell* ref)
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{
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this->hashidx_ = ref->hashidx_;
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this->ref_obj = ref;
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}
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Yosys::RTLIL::Cell* get_cpp_obj() const
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{
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Yosys::RTLIL::Cell* ret = Yosys::RTLIL::Cell::get_all_cells()->at(this->hashidx_);
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if(ret != NULL && ret == this->ref_obj)
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return ret;
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return NULL;
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}
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//WRAPPED bool hasPort(RTLIL::IdString portname) const;
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bool hasPort(IdString *portname);
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//WRAPPED void unsetPort(RTLIL::IdString portname);
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void unsetPort(IdString *portname);
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//WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal);
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void setPort(IdString *portname, SigSpec *signal);
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//WRAPPED bool input(RTLIL::IdString portname) const;
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bool input(IdString *portname);
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//WRAPPED bool output(RTLIL::IdString portname) const;
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bool output(IdString *portname);
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//WRAPPED bool hasParam(RTLIL::IdString paramname) const;
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bool hasParam(IdString *paramname);
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//WRAPPED void unsetParam(RTLIL::IdString paramname);
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void unsetParam(IdString *paramname);
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//WRAPPED void setParam(RTLIL::IdString paramname, RTLIL::Const value);
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void setParam(IdString *paramname, Const *value);
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//WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);
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void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);
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};
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std::ostream &operator<<(std::ostream &ostr, const Cell &ref)
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{
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if(ref.get_cpp_obj() != NULL)
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ostr << "Cell with name " << ref.get_cpp_obj()->name.c_str();
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else
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ostr << "deleted Cell";
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return ostr;
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}
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struct Wire
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{
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unsigned int hashidx_;
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Yosys::RTLIL::Wire* ref_obj;
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Wire(Yosys::RTLIL::Wire* ref)
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{
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this->hashidx_ = ref->hashidx_;
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this->ref_obj = ref;
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}
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Yosys::RTLIL::Wire* get_cpp_obj() const
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{
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Yosys::RTLIL::Wire* ret = Yosys::RTLIL::Wire::get_all_wires()->at(this->hashidx_);
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if(ret != NULL && ret == this->ref_obj)
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return ret;
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return NULL;
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}
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};
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std::ostream &operator<<(std::ostream &ostr, const Wire &ref)
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{
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if(ref.get_cpp_obj() != NULL)
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ostr << "Wire with name " << ref.get_cpp_obj()->name.c_str();
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else
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ostr << "deleted Wire";
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return ostr;
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}
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struct Memory
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{
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unsigned int hashidx_;
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Yosys::RTLIL::Memory* ref_obj;
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Memory(Yosys::RTLIL::Memory* ref)
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{
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this->hashidx_ = ref->hashidx_;
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this->ref_obj = ref;
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}
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Yosys::RTLIL::Memory* get_cpp_obj() const
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{
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Yosys::RTLIL::Memory* ret = Yosys::RTLIL::Memory::get_all_memorys()->at(this->hashidx_);
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if(ret != NULL && ret == this->ref_obj)
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return ret;
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return NULL;
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}
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};
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std::ostream &operator<<(std::ostream &ostr, const Memory &ref)
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{
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if(ref.get_cpp_obj() != NULL)
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ostr << "Memory with name " << ref.get_cpp_obj()->name.c_str();
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else
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ostr << "deleted Memory";
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return ostr;
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}
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struct Module
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{
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unsigned int hashidx_;
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Yosys::RTLIL::Module* ref_obj;
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Module(Yosys::RTLIL::Module* ref = new Yosys::RTLIL::Module())
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{
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this->hashidx_ = ref->hashidx_;
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this->ref_obj = ref;
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}
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Yosys::RTLIL::Module* get_cpp_obj() const
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{
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Yosys::RTLIL::Module* ret = Yosys::RTLIL::Module::get_all_modules()->at(this->hashidx_);
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if(ret != NULL && ret == this->ref_obj)
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return ret;
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|
return NULL;
|
|
}
|
|
|
|
boost::python::list get_cells()
|
|
{
|
|
Yosys::RTLIL::Module* cpp_obj = get_cpp_obj();
|
|
boost::python::list result;
|
|
if(cpp_obj == NULL)
|
|
{
|
|
return result;
|
|
}
|
|
for(auto &mod_it : cpp_obj->cells_)
|
|
{
|
|
result.append(new Cell(mod_it.second));
|
|
}
|
|
return result;
|
|
}
|
|
|
|
boost::python::list get_wires()
|
|
{
|
|
Yosys::RTLIL::Module* cpp_obj = get_cpp_obj();
|
|
boost::python::list result;
|
|
if(cpp_obj == NULL)
|
|
{
|
|
return result;
|
|
}
|
|
for(auto &mod_it : cpp_obj->wires_)
|
|
{
|
|
result.append(new Wire(mod_it.second));
|
|
}
|
|
return result;
|
|
}
|
|
|
|
void register_monitor(Monitor* const m);
|
|
|
|
//WRAPPED void connect(const RTLIL::SigSig &conn);
|
|
void connect_SigSig(PyObject *conn);
|
|
|
|
//WRAPPED void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
|
|
void connect_SigSpec_SigSpec(SigSpec *lhs, SigSpec *rhs);
|
|
|
|
//WRAPPED void new_connections(const std::vector<RTLIL::SigSig> &new_conn);
|
|
void new_connections(boost::python::list *new_conn);
|
|
|
|
//WRAPPED void cloneInto(RTLIL::Module *new_mod) const;
|
|
void cloneInto(Module *new_mod);
|
|
|
|
//WRAPPED void remove(const pool<RTLIL::Wire*> &wires);
|
|
void remove_pool_Wire(boost::python::list *wires);
|
|
|
|
//WRAPPED void remove(RTLIL::Cell *cell);
|
|
void remove_Cell(Cell *cell);
|
|
|
|
//WRAPPED void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
|
|
void rename_Wire_IdString(Wire *wire, IdString *new_name);
|
|
|
|
//WRAPPED void rename(RTLIL::Cell *cell, RTLIL::IdString new_name);
|
|
void rename_Cell_IdString(Cell *cell, IdString *new_name);
|
|
|
|
//WRAPPED void rename(RTLIL::IdString old_name, RTLIL::IdString new_name);
|
|
void rename_IdString_IdString(IdString *old_name, IdString *new_name);
|
|
|
|
//WRAPPED void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);
|
|
void swap_names_Wire_Wire(Wire *w1, Wire *w2);
|
|
|
|
//WRAPPED void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);
|
|
void swap_names_Cell_Cell(Cell *c1, Cell *c2);
|
|
|
|
//WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name);
|
|
IdString uniquify_IdString(IdString *name);
|
|
|
|
//WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name, int &index);
|
|
IdString uniquify_IdString_int(IdString *name, int index);
|
|
|
|
//WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
|
|
Wire addWire_IdString_int(IdString *name, int width = 1);
|
|
|
|
//WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
|
|
Wire addWire_IdString_Wire(IdString *name, Wire *other);
|
|
|
|
//WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
|
|
Cell addCell_IdString_IdString(IdString *name, IdString *type);
|
|
|
|
//WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
|
|
Cell addCell_IdString_Cell(IdString *name, Cell *other);
|
|
|
|
//WRAPPED RTLIL::Cell* addNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addPos(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addPos(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addNeg(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addNeg(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addXor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addReduceAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addReduceOr(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addReduceXor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addReduceXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addReduceBool(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addShl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addShl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addShr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addShr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addSshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addSshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addSshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addSshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addShift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addShift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addShiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addShiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addLt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addLt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addLe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addLe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addEq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addEq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addNe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addNe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addEqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addEqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addNex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addNex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addGe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addGe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addGt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addGt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addAdd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addAdd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addSub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addSub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addMul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addMul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addDiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addDiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addMod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addMod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = "");
|
|
Cell addPow(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool a_signed = false, bool b_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addLogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addLogicNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addLogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addLogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addLogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell addLogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addMux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = "");
|
|
Cell addMux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addPmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = "");
|
|
Cell addPmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src = "");
|
|
Cell addSlice(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *offset, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = "");
|
|
Cell addConcat(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src = "");
|
|
Cell addLut(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *lut, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src = "");
|
|
Cell addTribuf(IdString *name, SigSpec *sig_a, SigSpec *sig_en, SigSpec *sig_y, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = "");
|
|
Cell addAssert(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = "");
|
|
Cell addAssume(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = "");
|
|
Cell addLive(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = "");
|
|
Cell addFair(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = "");
|
|
Cell addCover(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = "");
|
|
Cell addEquiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
|
|
Cell addSr(IdString *name, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_q, bool set_polarity = true, bool clr_polarity = true, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = "");
|
|
Cell addFf(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = "");
|
|
Cell addDff(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = "");
|
|
Cell addDffe(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool en_polarity = true, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = "");
|
|
Cell addDlatch(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, std::string src = "");
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//WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = "");
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Cell addBufGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src = "");
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//WRAPPED RTLIL::Cell* addNotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = "");
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Cell addNotGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src = "");
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//WRAPPED RTLIL::Cell* addAndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
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Cell addAndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = "");
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//WRAPPED RTLIL::Cell* addNandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
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Cell addNandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = "");
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//WRAPPED RTLIL::Cell* addOrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
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Cell addOrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = "");
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//WRAPPED RTLIL::Cell* addNorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
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Cell addNorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = "");
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//WRAPPED RTLIL::Cell* addXorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
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Cell addXorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = "");
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//WRAPPED RTLIL::Cell* addXnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
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Cell addXnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = "");
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//WRAPPED RTLIL::Cell* addAndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
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Cell addAndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = "");
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//WRAPPED RTLIL::Cell* addOrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
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Cell addOrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = "");
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//WRAPPED RTLIL::Cell* addMuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = "");
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Cell addMuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, SigBit *sig_y, std::string src = "");
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//WRAPPED RTLIL::Cell* addAoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = "");
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Cell addAoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src = "");
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//WRAPPED RTLIL::Cell* addOai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = "");
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Cell addOai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src = "");
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//WRAPPED RTLIL::Cell* addAoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = "");
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Cell addAoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src = "");
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//WRAPPED RTLIL::Cell* addOai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = "");
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Cell addOai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src = "");
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//WRAPPED RTLIL::Cell* addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = "");
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Cell addFfGate(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src = "");
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//WRAPPED RTLIL::Cell* addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = "");
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Cell addDffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, std::string src = "");
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//WRAPPED RTLIL::Cell* addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = "");
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Cell addDffeGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool en_polarity = true, std::string src = "");
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//WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = "");
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Cell addDlatchGate(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, std::string src = "");
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//WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
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SigSpec Not(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Pos(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
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SigSpec Pos(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Neg(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
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SigSpec Neg(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec And(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec And(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Or(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Or(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Xor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Xor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Xnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Xnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec ReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
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SigSpec ReduceAnd(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec ReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
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SigSpec ReduceOr(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec ReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
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SigSpec ReduceXor(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec ReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
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SigSpec ReduceXnor(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec ReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
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SigSpec ReduceBool(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Shl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Shl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Shr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Shr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Sshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Sshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Sshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Sshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Shift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Shift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Shiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Shiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Lt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Lt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Le(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Le(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Eq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Eq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Ne(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Ne(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Eqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Eqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Nex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Nex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Ge(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Ge(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Gt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Gt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Add(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Add(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Sub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Sub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Mul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Mul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Div(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Div(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Mod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec Mod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec LogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
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SigSpec LogicNot(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec LogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec LogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec LogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
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SigSpec LogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = "");
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//WRAPPED RTLIL::SigSpec Mux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = "");
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SigSpec Mux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src = "");
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//WRAPPED RTLIL::SigSpec Pmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = "");
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SigSpec Pmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src = "");
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//WRAPPED RTLIL::SigBit BufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = "");
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SigBit BufGate(IdString *name, SigBit *sig_a, std::string src = "");
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//WRAPPED RTLIL::SigBit NotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = "");
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SigBit NotGate(IdString *name, SigBit *sig_a, std::string src = "");
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//WRAPPED RTLIL::SigBit AndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
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SigBit AndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = "");
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//WRAPPED RTLIL::SigBit NandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
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SigBit NandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = "");
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//WRAPPED RTLIL::SigBit OrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
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SigBit OrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = "");
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//WRAPPED RTLIL::SigBit NorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
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SigBit NorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = "");
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//WRAPPED RTLIL::SigBit XorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
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SigBit XorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = "");
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//WRAPPED RTLIL::SigBit XnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
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SigBit XnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = "");
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//WRAPPED RTLIL::SigBit AndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
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SigBit AndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = "");
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//WRAPPED RTLIL::SigBit OrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
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SigBit OrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = "");
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//WRAPPED RTLIL::SigBit MuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = "");
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SigBit MuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, std::string src = "");
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//WRAPPED RTLIL::SigBit Aoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = "");
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SigBit Aoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src = "");
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//WRAPPED RTLIL::SigBit Oai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = "");
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SigBit Oai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src = "");
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//WRAPPED RTLIL::SigBit Aoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = "");
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SigBit Aoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src = "");
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//WRAPPED RTLIL::SigBit Oai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = "");
|
|
SigBit Oai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::SigSpec Anyconst(RTLIL::IdString name, int width = 1, const std::string &src = "");
|
|
SigSpec Anyconst(IdString *name, int width = 1, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::SigSpec Anyseq(RTLIL::IdString name, int width = 1, const std::string &src = "");
|
|
SigSpec Anyseq(IdString *name, int width = 1, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::SigSpec Allconst(RTLIL::IdString name, int width = 1, const std::string &src = "");
|
|
SigSpec Allconst(IdString *name, int width = 1, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::SigSpec Allseq(RTLIL::IdString name, int width = 1, const std::string &src = "");
|
|
SigSpec Allseq(IdString *name, int width = 1, std::string src = "");
|
|
|
|
//WRAPPED RTLIL::SigSpec Initstate(RTLIL::IdString name, const std::string &src = "");
|
|
SigSpec Initstate(IdString *name, std::string src = "");
|
|
};
|
|
|
|
std::ostream &operator<<(std::ostream &ostr, const Module &ref)
|
|
{
|
|
if(ref.get_cpp_obj() != NULL)
|
|
ostr << "Module with name " << ref.get_cpp_obj()->name.c_str();
|
|
else
|
|
ostr << "deleted Module";
|
|
return ostr;
|
|
}
|
|
struct Design
|
|
{
|
|
unsigned int hashidx_;
|
|
Yosys::RTLIL::Design* ref_obj;
|
|
|
|
Design(Yosys::RTLIL::Design* ref = new Yosys::RTLIL::Design())
|
|
{
|
|
this->hashidx_ = ref->hashidx_;
|
|
this->ref_obj = ref;
|
|
}
|
|
|
|
Yosys::RTLIL::Design* get_cpp_obj() const
|
|
{
|
|
Yosys::RTLIL::Design* ret = Yosys::RTLIL::Design::get_all_designs()->at(this->hashidx_);
|
|
if(ret != NULL && ret == this->ref_obj)
|
|
return ret;
|
|
return NULL;
|
|
}
|
|
|
|
boost::python::list get_modules()
|
|
{
|
|
Yosys::RTLIL::Design* cpp_obj = get_cpp_obj();
|
|
boost::python::list result;
|
|
if(cpp_obj == NULL)
|
|
{
|
|
return result;
|
|
}
|
|
for(auto &mod_it : cpp_obj->modules_)
|
|
{
|
|
result.append(new Module(mod_it.second));
|
|
}
|
|
return result;
|
|
}
|
|
|
|
void run(std::string command)
|
|
{
|
|
Yosys::RTLIL::Design* cpp_design = get_cpp_obj();
|
|
if(cpp_design != NULL)
|
|
Yosys::run_pass(command, cpp_design);
|
|
|
|
}
|
|
|
|
void register_monitor(Monitor* const m);
|
|
|
|
//WRAPPED RTLIL::Module *module(RTLIL::IdString name);
|
|
Module module(IdString *name);
|
|
|
|
//WRAPPED bool has(RTLIL::IdString id) const {
|
|
bool has(IdString *id);
|
|
|
|
//WRAPPED void add(RTLIL::Module *module);
|
|
void add(Module *module);
|
|
|
|
//WRAPPED RTLIL::Module *addModule(RTLIL::IdString name);
|
|
Module addModule(IdString *name);
|
|
|
|
//WRAPPED void remove(RTLIL::Module *module);
|
|
void remove(Module *module);
|
|
|
|
//WRAPPED void rename(RTLIL::Module *module, RTLIL::IdString new_name);
|
|
void rename(Module *module, IdString *new_name);
|
|
|
|
//WRAPPED void scratchpad_unset(std::string varname);
|
|
void scratchpad_unset(std::string varname);
|
|
|
|
//WRAPPED void scratchpad_set_int(std::string varname, int value);
|
|
void scratchpad_set_int(std::string varname, int value);
|
|
|
|
//WRAPPED void scratchpad_set_bool(std::string varname, bool value);
|
|
void scratchpad_set_bool(std::string varname, bool value);
|
|
|
|
//WRAPPED void scratchpad_set_string(std::string varname, std::string value);
|
|
void scratchpad_set_string(std::string varname, std::string value);
|
|
|
|
//WRAPPED int scratchpad_get_int(std::string varname, int default_value = 0) const;
|
|
int scratchpad_get_int(std::string varname, int default_value = 0);
|
|
|
|
//WRAPPED bool scratchpad_get_bool(std::string varname, bool default_value = false) const;
|
|
bool scratchpad_get_bool(std::string varname, bool default_value = false);
|
|
|
|
//WRAPPED std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const;
|
|
std::string scratchpad_get_string(std::string varname, std::string default_value = std::string());
|
|
|
|
//WRAPPED bool selected_module(RTLIL::IdString mod_name) const;
|
|
bool selected_module_IdString(IdString *mod_name);
|
|
|
|
//WRAPPED bool selected_whole_module(RTLIL::IdString mod_name) const;
|
|
bool selected_whole_module_IdString(IdString *mod_name);
|
|
|
|
//WRAPPED bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const;
|
|
bool selected_member(IdString *mod_name, IdString *memb_name);
|
|
|
|
//WRAPPED bool selected_module(RTLIL::Module *mod) const;
|
|
bool selected_module_Module(Module *mod);
|
|
|
|
//WRAPPED bool selected_whole_module(RTLIL::Module *mod) const;
|
|
bool selected_whole_module_Module(Module *mod);
|
|
};
|
|
|
|
std::ostream &operator<<(std::ostream &ostr, const Design &ref)
|
|
{
|
|
if(ref.get_cpp_obj() != NULL)
|
|
ostr << "Design with identifier " << ref.hashidx_;
|
|
else
|
|
ostr << "deleted Design";
|
|
return ostr;
|
|
}
|
|
|
|
//WRAPPED static inline std::string escape_id(std::string str) {
|
|
inline std::string escape_id(std::string str)
|
|
{
|
|
return Yosys::RTLIL::escape_id(str);
|
|
}
|
|
|
|
//WRAPPED static inline std::string unescape_id(std::string str) {
|
|
inline std::string unescape_id_std_string(std::string str)
|
|
{
|
|
return Yosys::RTLIL::unescape_id(str);
|
|
}
|
|
|
|
//WRAPPED static inline std::string unescape_id(RTLIL::IdString str) {
|
|
inline std::string unescape_id_IdString(IdString *str)
|
|
{
|
|
return Yosys::RTLIL::unescape_id(*str->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_not(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_not(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_xor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_xor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_xnor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_xnor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_reduce_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_reduce_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_reduce_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_reduce_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_reduce_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_reduce_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_reduce_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_reduce_xor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_reduce_xor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_reduce_xnor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_reduce_xnor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_reduce_bool(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_reduce_bool(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_reduce_bool(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_logic_not(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_logic_not(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_logic_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_logic_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_logic_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_logic_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_shl(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_shl(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_shr(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_shr(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_sshl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_sshl(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_sshl(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_sshr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_sshr(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_sshr(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_shift(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_shift(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_shift(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_shiftx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_shiftx(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_shiftx(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_lt(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_lt(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_le(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_le(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_eq(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_eq(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_ne(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_ne(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_eqx(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_eqx(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_nex(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_nex(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_nex(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_ge(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_ge(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_gt(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_gt(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_add(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_add(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_sub(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_sub(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_mul(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_mul(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_div(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_div(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_mod(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_mod(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_pow(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_pow(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_pos(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_pos(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_pos(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Const const_neg(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
Const const_neg(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len)
|
|
{
|
|
return Const(Yosys::RTLIL::const_neg(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len));
|
|
}
|
|
|
|
struct Monitor : public Yosys::RTLIL::Monitor
|
|
{
|
|
|
|
virtual void notify_module_add(Yosys::RTLIL::Module *module) YS_OVERRIDE
|
|
{
|
|
py_notify_module_add(new Module(module));
|
|
}
|
|
|
|
virtual void notify_module_del(Yosys::RTLIL::Module *module) YS_OVERRIDE
|
|
{
|
|
py_notify_module_del(new Module(module));
|
|
}
|
|
|
|
virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE
|
|
{
|
|
Yosys::RTLIL::IdString *tmp_port = new Yosys::RTLIL::IdString(port);
|
|
Yosys::RTLIL::SigSpec *tmp_old_sig = new Yosys::RTLIL::SigSpec(old_sig);
|
|
py_notify_connect_cell(new Cell(cell), new IdString(tmp_port), new SigSpec(tmp_old_sig), new SigSpec(&sig));
|
|
delete tmp_port;
|
|
delete tmp_old_sig;
|
|
}
|
|
|
|
virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE
|
|
{
|
|
Yosys::RTLIL::SigSpec *first = new Yosys::RTLIL::SigSpec(sigsig.first);
|
|
Yosys::RTLIL::SigSpec *second = new Yosys::RTLIL::SigSpec(sigsig.second);
|
|
py_notify_connect_tuple(new Module(module), boost::python::make_tuple(new SigSpec(first), new SigSpec(second)));
|
|
delete first;
|
|
delete second;
|
|
}
|
|
|
|
virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector<Yosys::RTLIL::SigSig> &sigsig_vec) YS_OVERRIDE
|
|
{
|
|
boost::python::list sigsig_list;
|
|
for(auto sigsig : sigsig_vec)
|
|
sigsig_list.append(boost::python::make_tuple(new SigSpec(&sigsig.first), new SigSpec(&sigsig.second)));
|
|
py_notify_connect_list(new Module(module), sigsig_list);
|
|
}
|
|
|
|
virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE
|
|
{
|
|
py_notify_blackout(new Module(module));
|
|
}
|
|
|
|
virtual void py_notify_module_add(Module*){};
|
|
virtual void py_notify_module_del(Module*){};
|
|
virtual void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig){};
|
|
virtual void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig){};
|
|
virtual void py_notify_connect_list(Module* module, boost::python::list sigsig_list){};
|
|
virtual void py_notify_blackout(Module*){};
|
|
};
|
|
|
|
struct MonitorWrap : Monitor, boost::python::wrapper<Monitor>
|
|
{
|
|
void py_notify_module_add(Module* m)
|
|
{
|
|
if(boost::python::override py_notify_module_add = this->get_override("py_notify_module_add"))
|
|
py_notify_module_add(m);
|
|
else
|
|
Monitor::py_notify_module_add(m);
|
|
}
|
|
|
|
void default_py_notify_module_add(Module* m)
|
|
{
|
|
this->Monitor::py_notify_module_add(m);
|
|
}
|
|
|
|
void py_notify_module_del(Module* m)
|
|
{
|
|
if(boost::python::override py_notify_module_del = this->get_override("py_notify_module_del"))
|
|
py_notify_module_del(m);
|
|
else
|
|
Monitor::py_notify_module_del(m);
|
|
}
|
|
|
|
void default_py_notify_module_del(Module* m)
|
|
{
|
|
this->Monitor::py_notify_module_del(m);
|
|
}
|
|
|
|
void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig)
|
|
{
|
|
if(boost::python::override py_notify_connect_cell = this->get_override("py_notify_connect_cell"))
|
|
py_notify_connect_cell(cell, port, old_sig, sig);
|
|
else
|
|
Monitor::py_notify_connect_cell(cell, port, old_sig, sig);
|
|
}
|
|
|
|
void default_py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig)
|
|
{
|
|
this->Monitor::py_notify_connect_cell(cell, port, old_sig, sig);
|
|
}
|
|
|
|
void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig)
|
|
{
|
|
if(boost::python::override py_notify_connect_tuple = this->get_override("py_notify_connect_tuple"))
|
|
py_notify_connect_tuple(module, sigsig);
|
|
else
|
|
Monitor::py_notify_connect_tuple(module, sigsig);
|
|
}
|
|
|
|
void default_py_notify_connect_tuple(Module *module, boost::python::tuple sigsig)
|
|
{
|
|
this->Monitor::py_notify_connect_tuple(module, sigsig);
|
|
}
|
|
|
|
void py_notify_connect_list(Module* module, boost::python::list sigsig_list)
|
|
{
|
|
if(boost::python::override py_notify_connect_list = this->get_override("py_notify_connect_list"))
|
|
py_notify_connect_list(module, sigsig_list);
|
|
else
|
|
Monitor::py_notify_connect_list(module, sigsig_list);
|
|
}
|
|
|
|
void default_py_notify_connect_list(Module* module, boost::python::list sigsig_list)
|
|
{
|
|
this->Monitor::py_notify_connect_list(module, sigsig_list);
|
|
}
|
|
|
|
void py_notify_blackout(Module* m)
|
|
{
|
|
if(boost::python::override py_notify_blackout = this->get_override("py_notify_blackout"))
|
|
py_notify_blackout(m);
|
|
else
|
|
Monitor::py_notify_blackout(m);
|
|
}
|
|
|
|
void default_py_notify_blackout(Module* m)
|
|
{
|
|
this->Monitor::py_notify_blackout(m);
|
|
}
|
|
};
|
|
|
|
struct PyPass : public Yosys::Pass
|
|
{
|
|
PyPass(std::string name, std::string short_help) : Yosys::Pass(name, short_help) { }
|
|
|
|
virtual void execute(vector<string> args, Yosys::RTLIL::Design* d) YS_OVERRIDE
|
|
{
|
|
boost::python::list py_args;
|
|
for(auto arg : args)
|
|
py_args.append(arg);
|
|
py_execute(py_args, new Design(d));
|
|
}
|
|
|
|
virtual void help() YS_OVERRIDE
|
|
{
|
|
py_help();
|
|
}
|
|
|
|
virtual void py_execute(boost::python::list args, Design* d){}
|
|
virtual void py_help(){}
|
|
};
|
|
|
|
struct PassWrap : PyPass, boost::python::wrapper<PyPass>
|
|
{
|
|
|
|
PassWrap(std::string name, std::string short_help) : PyPass(name, short_help) { }
|
|
|
|
void py_execute(boost::python::list args, Design* d)
|
|
{
|
|
if(boost::python::override py_execute = this->get_override("py_execute"))
|
|
py_execute(args, d);
|
|
else
|
|
PyPass::py_execute(args, d);
|
|
}
|
|
|
|
void default_py_execute(boost::python::list args, Design* d)
|
|
{
|
|
this->PyPass::py_execute(args, d);
|
|
}
|
|
|
|
void py_help()
|
|
{
|
|
if(boost::python::override py_help = this->get_override("py_help"))
|
|
py_help();
|
|
else
|
|
PyPass::py_help();
|
|
}
|
|
|
|
void default_py_help()
|
|
{
|
|
this->PyPass::py_help();
|
|
}
|
|
};
|
|
|
|
void Module::register_monitor(Monitor* const m)
|
|
{
|
|
Yosys::RTLIL::Module* cpp_module = this->get_cpp_obj();
|
|
if(cpp_module == NULL)
|
|
return;
|
|
cpp_module->monitors.insert(m);
|
|
}
|
|
|
|
void Design::register_monitor(Monitor* const m)
|
|
{
|
|
Yosys::RTLIL::Design* cpp_design = this->get_cpp_obj();
|
|
if(cpp_design == NULL)
|
|
return;
|
|
cpp_design->monitors.insert(m);
|
|
}
|
|
|
|
//WRAPPED static inline int get_reference(int idx)
|
|
inline int IdString::get_reference(int idx)
|
|
{
|
|
return Yosys::RTLIL::IdString::get_reference(idx);
|
|
}
|
|
|
|
//WRAPPED static inline void put_reference(int idx)
|
|
inline void IdString::put_reference(int idx)
|
|
{
|
|
Yosys::RTLIL::IdString::put_reference(idx);
|
|
}
|
|
|
|
//WRAPPED bool in(IdString rhs) const { return *this == rhs; }
|
|
bool IdString::in_IdString(IdString *rhs)
|
|
{
|
|
return this->get_cpp_obj()->in(*rhs->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED bool in(const std::string &rhs) const { return *this == rhs; }
|
|
bool IdString::in_std_string(std::string rhs)
|
|
{
|
|
return this->get_cpp_obj()->in(rhs);
|
|
}
|
|
|
|
//WRAPPED int as_int(bool is_signed = false) const;
|
|
int Const::as_int(bool is_signed)
|
|
{
|
|
return this->get_cpp_obj()->as_int(is_signed);
|
|
}
|
|
|
|
//WRAPPED static Const from_string(std::string str);
|
|
Const Const::from_string(std::string str)
|
|
{
|
|
return Const(Yosys::RTLIL::Const::from_string(str));
|
|
}
|
|
|
|
//WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const {
|
|
inline Const Const::extract(int offset, int len, State padding)
|
|
{
|
|
return Const(this->get_cpp_obj()->extract(offset, len, padding));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigChunk extract(int offset, int length) const;
|
|
SigChunk SigChunk::extract(int offset, int length)
|
|
{
|
|
return SigChunk(this->get_cpp_obj()->extract(offset, length));
|
|
}
|
|
|
|
//WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);
|
|
void SigSpec::replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with)
|
|
{
|
|
this->get_cpp_obj()->replace(*pattern->get_cpp_obj(), *with->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;
|
|
void SigSpec::replace_SigSpec_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with, SigSpec *other)
|
|
{
|
|
this->get_cpp_obj()->replace(*pattern->get_cpp_obj(), *with->get_cpp_obj(), other->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void replace(int offset, const RTLIL::SigSpec &with);
|
|
void SigSpec::replace_int_SigSpec(int offset, SigSpec *with)
|
|
{
|
|
this->get_cpp_obj()->replace(offset, *with->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void remove(const RTLIL::SigSpec &pattern);
|
|
void SigSpec::remove_SigSpec(SigSpec *pattern)
|
|
{
|
|
this->get_cpp_obj()->remove(*pattern->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;
|
|
void SigSpec::remove_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other)
|
|
{
|
|
this->get_cpp_obj()->remove(*pattern->get_cpp_obj(), other->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);
|
|
void SigSpec::remove2_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other)
|
|
{
|
|
this->get_cpp_obj()->remove2(*pattern->get_cpp_obj(), other->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void remove(const pool<RTLIL::SigBit> &pattern);
|
|
void SigSpec::remove_pool_SigBit(boost::python::list *pattern)
|
|
{
|
|
pool<Yosys::RTLIL::SigBit> pattern_;
|
|
for(int i = 0; i < len(*pattern); ++i)
|
|
{
|
|
}
|
|
this->get_cpp_obj()->remove(pattern_);
|
|
}
|
|
|
|
//WRAPPED void remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;
|
|
void SigSpec::remove_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other)
|
|
{
|
|
pool<Yosys::RTLIL::SigBit> pattern_;
|
|
for(int i = 0; i < len(*pattern); ++i)
|
|
{
|
|
}
|
|
this->get_cpp_obj()->remove(pattern_, other->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);
|
|
void SigSpec::remove2_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other)
|
|
{
|
|
pool<Yosys::RTLIL::SigBit> pattern_;
|
|
for(int i = 0; i < len(*pattern); ++i)
|
|
{
|
|
}
|
|
this->get_cpp_obj()->remove2(pattern_, other->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void remove(int offset, int length = 1);
|
|
void SigSpec::remove_int_int(int offset, int length)
|
|
{
|
|
this->get_cpp_obj()->remove(offset, length);
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;
|
|
SigSpec SigSpec::extract_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->extract(*pattern->get_cpp_obj(), other->get_cpp_obj()));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;
|
|
SigSpec SigSpec::extract_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other)
|
|
{
|
|
pool<Yosys::RTLIL::SigBit> pattern_;
|
|
for(int i = 0; i < len(*pattern); ++i)
|
|
{
|
|
}
|
|
return SigSpec(this->get_cpp_obj()->extract(pattern_, other->get_cpp_obj()));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec extract(int offset, int length = 1) const;
|
|
SigSpec SigSpec::extract_int_int(int offset, int length)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->extract(offset, length));
|
|
}
|
|
|
|
//WRAPPED void append(const RTLIL::SigSpec &signal);
|
|
void SigSpec::append(SigSpec *signal)
|
|
{
|
|
this->get_cpp_obj()->append(*signal->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void append_bit(const RTLIL::SigBit &bit);
|
|
void SigSpec::append_bit(SigBit *bit)
|
|
{
|
|
this->get_cpp_obj()->append_bit(*bit->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void extend_u0(int width, bool is_signed = false);
|
|
void SigSpec::extend_u0(int width, bool is_signed)
|
|
{
|
|
this->get_cpp_obj()->extend_u0(width, is_signed);
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec repeat(int num) const;
|
|
SigSpec SigSpec::repeat(int num)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->repeat(num));
|
|
}
|
|
|
|
//WRAPPED int as_int(bool is_signed = false) const;
|
|
int SigSpec::as_int(bool is_signed)
|
|
{
|
|
return this->get_cpp_obj()->as_int(is_signed);
|
|
}
|
|
|
|
//WRAPPED bool match(std::string pattern) const;
|
|
bool SigSpec::match(std::string pattern)
|
|
{
|
|
return this->get_cpp_obj()->match(pattern);
|
|
}
|
|
|
|
//WRAPPED static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);
|
|
bool SigSpec::parse(SigSpec *sig, Module *module, std::string str)
|
|
{
|
|
return Yosys::RTLIL::SigSpec::parse(*sig->get_cpp_obj(), module->get_cpp_obj(), str);
|
|
}
|
|
|
|
//WRAPPED static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);
|
|
bool SigSpec::parse_sel(SigSpec *sig, Design *design, Module *module, std::string str)
|
|
{
|
|
return Yosys::RTLIL::SigSpec::parse_sel(*sig->get_cpp_obj(), design->get_cpp_obj(), module->get_cpp_obj(), str);
|
|
}
|
|
|
|
//WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);
|
|
bool SigSpec::parse_rhs(SigSpec *lhs, SigSpec *sig, Module *module, std::string str)
|
|
{
|
|
return Yosys::RTLIL::SigSpec::parse_rhs(*lhs->get_cpp_obj(), *sig->get_cpp_obj(), module->get_cpp_obj(), str);
|
|
}
|
|
|
|
//WRAPPED bool hasPort(RTLIL::IdString portname) const;
|
|
bool Cell::hasPort(IdString *portname)
|
|
{
|
|
return this->get_cpp_obj()->hasPort(*portname->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void unsetPort(RTLIL::IdString portname);
|
|
void Cell::unsetPort(IdString *portname)
|
|
{
|
|
this->get_cpp_obj()->unsetPort(*portname->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal);
|
|
void Cell::setPort(IdString *portname, SigSpec *signal)
|
|
{
|
|
this->get_cpp_obj()->setPort(*portname->get_cpp_obj(), *signal->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED bool input(RTLIL::IdString portname) const;
|
|
bool Cell::input(IdString *portname)
|
|
{
|
|
return this->get_cpp_obj()->input(*portname->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED bool output(RTLIL::IdString portname) const;
|
|
bool Cell::output(IdString *portname)
|
|
{
|
|
return this->get_cpp_obj()->output(*portname->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED bool hasParam(RTLIL::IdString paramname) const;
|
|
bool Cell::hasParam(IdString *paramname)
|
|
{
|
|
return this->get_cpp_obj()->hasParam(*paramname->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void unsetParam(RTLIL::IdString paramname);
|
|
void Cell::unsetParam(IdString *paramname)
|
|
{
|
|
this->get_cpp_obj()->unsetParam(*paramname->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void setParam(RTLIL::IdString paramname, RTLIL::Const value);
|
|
void Cell::setParam(IdString *paramname, Const *value)
|
|
{
|
|
this->get_cpp_obj()->setParam(*paramname->get_cpp_obj(), *value->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);
|
|
void Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
|
|
{
|
|
this->get_cpp_obj()->fixup_parameters(set_a_signed, set_b_signed);
|
|
}
|
|
|
|
//WRAPPED void connect(const RTLIL::SigSig &conn);
|
|
void Module::connect_SigSig(PyObject* conn)
|
|
{
|
|
if(!PyTuple_Check(conn) or PyTuple_Size(conn) != 2)
|
|
throw std::logic_error("Tuple of two SigSpecs required");
|
|
SigSpec conn_sp0 = boost::python::extract<SigSpec>(PyTuple_GetItem(conn, 0));
|
|
SigSpec conn_sp1 = boost::python::extract<SigSpec>(PyTuple_GetItem(conn, 1));
|
|
Yosys::RTLIL::SigSig conn_(conn_sp0.get_cpp_obj(), conn_sp1.get_cpp_obj());
|
|
this->get_cpp_obj()->connect(conn_);
|
|
}
|
|
|
|
//WRAPPED void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
|
|
void Module::connect_SigSpec_SigSpec(SigSpec *lhs, SigSpec *rhs)
|
|
{
|
|
this->get_cpp_obj()->connect(*lhs->get_cpp_obj(), *rhs->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void new_connections(const std::vector<RTLIL::SigSig> &new_conn);
|
|
void Module::new_connections(boost::python::list *new_conn)
|
|
{
|
|
std::vector<Yosys::RTLIL::SigSig> new_conn_;
|
|
for(int i = 0; i < len(*new_conn); ++i)
|
|
{
|
|
}
|
|
this->get_cpp_obj()->new_connections(new_conn_);
|
|
}
|
|
|
|
//WRAPPED void cloneInto(RTLIL::Module *new_mod) const;
|
|
void Module::cloneInto(Module *new_mod)
|
|
{
|
|
this->get_cpp_obj()->cloneInto(new_mod->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void remove(const pool<RTLIL::Wire*> &wires);
|
|
void Module::remove_pool_Wire(boost::python::list *wires)
|
|
{
|
|
pool<Yosys::RTLIL::Wire*> wires_;
|
|
for(int i = 0; i < len(*wires); ++i)
|
|
{
|
|
}
|
|
this->get_cpp_obj()->remove(wires_);
|
|
}
|
|
|
|
//WRAPPED void remove(RTLIL::Cell *cell);
|
|
void Module::remove_Cell(Cell *cell)
|
|
{
|
|
this->get_cpp_obj()->remove(cell->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
|
|
void Module::rename_Wire_IdString(Wire *wire, IdString *new_name)
|
|
{
|
|
this->get_cpp_obj()->rename(wire->get_cpp_obj(), *new_name->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void rename(RTLIL::Cell *cell, RTLIL::IdString new_name);
|
|
void Module::rename_Cell_IdString(Cell *cell, IdString *new_name)
|
|
{
|
|
this->get_cpp_obj()->rename(cell->get_cpp_obj(), *new_name->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void rename(RTLIL::IdString old_name, RTLIL::IdString new_name);
|
|
void Module::rename_IdString_IdString(IdString *old_name, IdString *new_name)
|
|
{
|
|
this->get_cpp_obj()->rename(*old_name->get_cpp_obj(), *new_name->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);
|
|
void Module::swap_names_Wire_Wire(Wire *w1, Wire *w2)
|
|
{
|
|
this->get_cpp_obj()->swap_names(w1->get_cpp_obj(), w2->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);
|
|
void Module::swap_names_Cell_Cell(Cell *c1, Cell *c2)
|
|
{
|
|
this->get_cpp_obj()->swap_names(c1->get_cpp_obj(), c2->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name);
|
|
IdString Module::uniquify_IdString(IdString *name)
|
|
{
|
|
return IdString(this->get_cpp_obj()->uniquify(*name->get_cpp_obj()));
|
|
}
|
|
|
|
//WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name, int &index);
|
|
IdString Module::uniquify_IdString_int(IdString *name, int index)
|
|
{
|
|
return IdString(this->get_cpp_obj()->uniquify(*name->get_cpp_obj(), index));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
|
|
Wire Module::addWire_IdString_int(IdString *name, int width)
|
|
{
|
|
return Wire(this->get_cpp_obj()->addWire(*name->get_cpp_obj(), width));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
|
|
Wire Module::addWire_IdString_Wire(IdString *name, Wire *other)
|
|
{
|
|
return Wire(this->get_cpp_obj()->addWire(*name->get_cpp_obj(), other->get_cpp_obj()));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
|
|
Cell Module::addCell_IdString_IdString(IdString *name, IdString *type)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addCell(*name->get_cpp_obj(), *type->get_cpp_obj()));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
|
|
Cell Module::addCell_IdString_Cell(IdString *name, Cell *other)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addCell(*name->get_cpp_obj(), other->get_cpp_obj()));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addPos(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addPos(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addPos(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addNeg(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addNeg(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addNeg(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addXor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addReduceAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addReduceAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addReduceOr(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addReduceOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addReduceXor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addReduceXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addReduceXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addReduceXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addReduceBool(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addReduceBool(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addShl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addShl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addShl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addShr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addShr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addShr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addSshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addSshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addSshl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addSshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addSshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addSshr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addShift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addShift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addShift(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addShiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addShiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addShiftx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addLt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addLt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addLt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addLe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addLe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addLe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addEq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addEq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addEq(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addNe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addNe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addNe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addEqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addEqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addEqx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addNex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addNex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addNex(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addGe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addGe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addGe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addGt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addGt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addGt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addAdd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addAdd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addAdd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addSub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addSub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addSub(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addMul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addMul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addMul(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addDiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addDiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addDiv(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addMod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addMod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addMod(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = "");
|
|
Cell Module::addPow(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool a_signed, bool b_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addPow(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), a_signed, b_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addLogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addLogicNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addLogicNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addLogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addLogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addLogicAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addLogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = "");
|
|
Cell Module::addLogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addLogicOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addMux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = "");
|
|
Cell Module::addMux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addMux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addPmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = "");
|
|
Cell Module::addPmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addPmux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src = "");
|
|
Cell Module::addSlice(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *offset, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addSlice(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), *offset->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = "");
|
|
Cell Module::addConcat(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addConcat(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src = "");
|
|
Cell Module::addLut(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *lut, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addLut(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), *lut->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src = "");
|
|
Cell Module::addTribuf(IdString *name, SigSpec *sig_a, SigSpec *sig_en, SigSpec *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addTribuf(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = "");
|
|
Cell Module::addAssert(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addAssert(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = "");
|
|
Cell Module::addAssume(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addAssume(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = "");
|
|
Cell Module::addLive(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addLive(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = "");
|
|
Cell Module::addFair(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addFair(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = "");
|
|
Cell Module::addCover(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addCover(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = "");
|
|
Cell Module::addEquiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addEquiv(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
|
|
Cell Module::addSr(IdString *name, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_q, bool set_polarity, bool clr_polarity, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addSr(*name->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_q->get_cpp_obj(), set_polarity, clr_polarity, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = "");
|
|
Cell Module::addFf(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addFf(*name->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = "");
|
|
Cell Module::addDff(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addDff(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = "");
|
|
Cell Module::addDffe(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool en_polarity, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addDffe(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = "");
|
|
Cell Module::addDlatch(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addDlatch(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = "");
|
|
Cell Module::addBufGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addBufGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addNotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = "");
|
|
Cell Module::addNotGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addNotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addAndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
|
|
Cell Module::addAndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addAndGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addNandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
|
|
Cell Module::addNandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addNandGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addOrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
|
|
Cell Module::addOrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addOrGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addNorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
|
|
Cell Module::addNorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addNorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addXorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
|
|
Cell Module::addXorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addXorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addXnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
|
|
Cell Module::addXnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addXnorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addAndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
|
|
Cell Module::addAndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addAndnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addOrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = "");
|
|
Cell Module::addOrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addOrnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addMuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = "");
|
|
Cell Module::addMuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, SigBit *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addMuxGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addAoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = "");
|
|
Cell Module::addAoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addAoi3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addOai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = "");
|
|
Cell Module::addOai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addOai3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addAoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = "");
|
|
Cell Module::addAoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addAoi4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addOai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = "");
|
|
Cell Module::addOai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addOai4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_y->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = "");
|
|
Cell Module::addFfGate(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addFfGate(*name->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = "");
|
|
Cell Module::addDffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addDffGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = "");
|
|
Cell Module::addDffeGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool en_polarity, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addDffeGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = "");
|
|
Cell Module::addDlatchGate(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src)
|
|
{
|
|
return Cell(this->get_cpp_obj()->addDlatchGate(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Not(IdString *name, SigSpec *sig_a, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Not(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Pos(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Pos(IdString *name, SigSpec *sig_a, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Pos(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Neg(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Neg(IdString *name, SigSpec *sig_a, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Neg(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec And(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::And(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->And(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Or(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Or(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Or(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Xor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Xor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Xor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Xnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Xnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Xnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec ReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::ReduceAnd(IdString *name, SigSpec *sig_a, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->ReduceAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec ReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::ReduceOr(IdString *name, SigSpec *sig_a, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->ReduceOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec ReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::ReduceXor(IdString *name, SigSpec *sig_a, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->ReduceXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec ReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::ReduceXnor(IdString *name, SigSpec *sig_a, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->ReduceXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec ReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::ReduceBool(IdString *name, SigSpec *sig_a, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->ReduceBool(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Shl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Shl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Shl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Shr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Shr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Shr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Sshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Sshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Sshl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Sshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Sshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Sshr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Shift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Shift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Shift(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Shiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Shiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Shiftx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Lt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Lt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Lt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Le(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Le(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Le(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Eq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Eq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Eq(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Ne(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Ne(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Ne(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Eqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Eqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Eqx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Nex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Nex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Nex(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Ge(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Ge(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Ge(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Gt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Gt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Gt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Add(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Add(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Add(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Sub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Sub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Sub(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Mul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Mul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Mul(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Div(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Div(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Div(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Mod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::Mod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Mod(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec LogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::LogicNot(IdString *name, SigSpec *sig_a, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->LogicNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec LogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::LogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->LogicAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec LogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = "");
|
|
SigSpec Module::LogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->LogicOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Mux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = "");
|
|
SigSpec Module::Mux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Mux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Pmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = "");
|
|
SigSpec Module::Pmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Pmux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigBit BufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = "");
|
|
SigBit Module::BufGate(IdString *name, SigBit *sig_a, std::string src)
|
|
{
|
|
return SigBit(this->get_cpp_obj()->BufGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigBit NotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = "");
|
|
SigBit Module::NotGate(IdString *name, SigBit *sig_a, std::string src)
|
|
{
|
|
return SigBit(this->get_cpp_obj()->NotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigBit AndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
|
|
SigBit Module::AndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src)
|
|
{
|
|
return SigBit(this->get_cpp_obj()->AndGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigBit NandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
|
|
SigBit Module::NandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src)
|
|
{
|
|
return SigBit(this->get_cpp_obj()->NandGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigBit OrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
|
|
SigBit Module::OrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src)
|
|
{
|
|
return SigBit(this->get_cpp_obj()->OrGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigBit NorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
|
|
SigBit Module::NorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src)
|
|
{
|
|
return SigBit(this->get_cpp_obj()->NorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigBit XorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
|
|
SigBit Module::XorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src)
|
|
{
|
|
return SigBit(this->get_cpp_obj()->XorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigBit XnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
|
|
SigBit Module::XnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src)
|
|
{
|
|
return SigBit(this->get_cpp_obj()->XnorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigBit AndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
|
|
SigBit Module::AndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src)
|
|
{
|
|
return SigBit(this->get_cpp_obj()->AndnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigBit OrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = "");
|
|
SigBit Module::OrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src)
|
|
{
|
|
return SigBit(this->get_cpp_obj()->OrnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigBit MuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = "");
|
|
SigBit Module::MuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, std::string src)
|
|
{
|
|
return SigBit(this->get_cpp_obj()->MuxGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigBit Aoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = "");
|
|
SigBit Module::Aoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src)
|
|
{
|
|
return SigBit(this->get_cpp_obj()->Aoi3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigBit Oai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = "");
|
|
SigBit Module::Oai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src)
|
|
{
|
|
return SigBit(this->get_cpp_obj()->Oai3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigBit Aoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = "");
|
|
SigBit Module::Aoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src)
|
|
{
|
|
return SigBit(this->get_cpp_obj()->Aoi4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigBit Oai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = "");
|
|
SigBit Module::Oai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src)
|
|
{
|
|
return SigBit(this->get_cpp_obj()->Oai4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Anyconst(RTLIL::IdString name, int width = 1, const std::string &src = "");
|
|
SigSpec Module::Anyconst(IdString *name, int width, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Anyconst(*name->get_cpp_obj(), width, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Anyseq(RTLIL::IdString name, int width = 1, const std::string &src = "");
|
|
SigSpec Module::Anyseq(IdString *name, int width, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Anyseq(*name->get_cpp_obj(), width, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Allconst(RTLIL::IdString name, int width = 1, const std::string &src = "");
|
|
SigSpec Module::Allconst(IdString *name, int width, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Allconst(*name->get_cpp_obj(), width, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Allseq(RTLIL::IdString name, int width = 1, const std::string &src = "");
|
|
SigSpec Module::Allseq(IdString *name, int width, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Allseq(*name->get_cpp_obj(), width, src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::SigSpec Initstate(RTLIL::IdString name, const std::string &src = "");
|
|
SigSpec Module::Initstate(IdString *name, std::string src)
|
|
{
|
|
return SigSpec(this->get_cpp_obj()->Initstate(*name->get_cpp_obj(), src));
|
|
}
|
|
|
|
//WRAPPED RTLIL::Module *module(RTLIL::IdString name);
|
|
Module Design::module(IdString *name)
|
|
{
|
|
return Module(this->get_cpp_obj()->module(*name->get_cpp_obj()));
|
|
}
|
|
|
|
//WRAPPED bool has(RTLIL::IdString id) const {
|
|
bool Design::has(IdString *id)
|
|
{
|
|
return this->get_cpp_obj()->has(*id->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void add(RTLIL::Module *module);
|
|
void Design::add(Module *module)
|
|
{
|
|
this->get_cpp_obj()->add(module->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED RTLIL::Module *addModule(RTLIL::IdString name);
|
|
Module Design::addModule(IdString *name)
|
|
{
|
|
return Module(this->get_cpp_obj()->addModule(*name->get_cpp_obj()));
|
|
}
|
|
|
|
//WRAPPED void remove(RTLIL::Module *module);
|
|
void Design::remove(Module *module)
|
|
{
|
|
this->get_cpp_obj()->remove(module->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void rename(RTLIL::Module *module, RTLIL::IdString new_name);
|
|
void Design::rename(Module *module, IdString *new_name)
|
|
{
|
|
this->get_cpp_obj()->rename(module->get_cpp_obj(), *new_name->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED void scratchpad_unset(std::string varname);
|
|
void Design::scratchpad_unset(std::string varname)
|
|
{
|
|
this->get_cpp_obj()->scratchpad_unset(varname);
|
|
}
|
|
|
|
//WRAPPED void scratchpad_set_int(std::string varname, int value);
|
|
void Design::scratchpad_set_int(std::string varname, int value)
|
|
{
|
|
this->get_cpp_obj()->scratchpad_set_int(varname, value);
|
|
}
|
|
|
|
//WRAPPED void scratchpad_set_bool(std::string varname, bool value);
|
|
void Design::scratchpad_set_bool(std::string varname, bool value)
|
|
{
|
|
this->get_cpp_obj()->scratchpad_set_bool(varname, value);
|
|
}
|
|
|
|
//WRAPPED void scratchpad_set_string(std::string varname, std::string value);
|
|
void Design::scratchpad_set_string(std::string varname, std::string value)
|
|
{
|
|
this->get_cpp_obj()->scratchpad_set_string(varname, value);
|
|
}
|
|
|
|
//WRAPPED int scratchpad_get_int(std::string varname, int default_value = 0) const;
|
|
int Design::scratchpad_get_int(std::string varname, int default_value)
|
|
{
|
|
return this->get_cpp_obj()->scratchpad_get_int(varname, default_value);
|
|
}
|
|
|
|
//WRAPPED bool scratchpad_get_bool(std::string varname, bool default_value = false) const;
|
|
bool Design::scratchpad_get_bool(std::string varname, bool default_value)
|
|
{
|
|
return this->get_cpp_obj()->scratchpad_get_bool(varname, default_value);
|
|
}
|
|
|
|
//WRAPPED std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const;
|
|
std::string Design::scratchpad_get_string(std::string varname, std::string default_value)
|
|
{
|
|
return this->get_cpp_obj()->scratchpad_get_string(varname, default_value);
|
|
}
|
|
|
|
//WRAPPED bool selected_module(RTLIL::IdString mod_name) const;
|
|
bool Design::selected_module_IdString(IdString *mod_name)
|
|
{
|
|
return this->get_cpp_obj()->selected_module(*mod_name->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED bool selected_whole_module(RTLIL::IdString mod_name) const;
|
|
bool Design::selected_whole_module_IdString(IdString *mod_name)
|
|
{
|
|
return this->get_cpp_obj()->selected_whole_module(*mod_name->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const;
|
|
bool Design::selected_member(IdString *mod_name, IdString *memb_name)
|
|
{
|
|
return this->get_cpp_obj()->selected_member(*mod_name->get_cpp_obj(), *memb_name->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED bool selected_module(RTLIL::Module *mod) const;
|
|
bool Design::selected_module_Module(Module *mod)
|
|
{
|
|
return this->get_cpp_obj()->selected_module(mod->get_cpp_obj());
|
|
}
|
|
|
|
//WRAPPED bool selected_whole_module(RTLIL::Module *mod) const;
|
|
bool Design::selected_whole_module_Module(Module *mod)
|
|
{
|
|
return this->get_cpp_obj()->selected_whole_module(mod->get_cpp_obj());
|
|
}
|
|
|
|
struct Initializer
|
|
{
|
|
Initializer() {
|
|
if(!Yosys::yosys_already_setup())
|
|
{
|
|
Yosys::log_streams.push_back(&std::cout);
|
|
Yosys::log_error_stderr = true;
|
|
Yosys::yosys_setup();
|
|
Yosys::yosys_banner();
|
|
}
|
|
}
|
|
|
|
Initializer(Initializer const &) {}
|
|
|
|
~Initializer() {
|
|
Yosys::yosys_shutdown();
|
|
}
|
|
};
|
|
|
|
BOOST_PYTHON_MODULE(libyosys)
|
|
{
|
|
using namespace boost::python;
|
|
|
|
enum_<Yosys::RTLIL::State>("State")
|
|
.value("S0",Yosys::RTLIL::S0)
|
|
.value("S1",Yosys::RTLIL::S1)
|
|
.value("Sx",Yosys::RTLIL::Sx)
|
|
.value("Sz",Yosys::RTLIL::Sz)
|
|
.value("Sa",Yosys::RTLIL::Sa)
|
|
.value("Sm",Yosys::RTLIL::Sm)
|
|
;
|
|
|
|
enum_<Yosys::RTLIL::SyncType>("SyncType")
|
|
.value("ST0",Yosys::RTLIL::ST0)
|
|
.value("ST1",Yosys::RTLIL::ST1)
|
|
.value("STp",Yosys::RTLIL::STp)
|
|
.value("STn",Yosys::RTLIL::STn)
|
|
.value("STe",Yosys::RTLIL::STe)
|
|
.value("STa",Yosys::RTLIL::STa)
|
|
.value("STg",Yosys::RTLIL::STg)
|
|
.value("STi",Yosys::RTLIL::STi)
|
|
;
|
|
|
|
enum_<Yosys::RTLIL::ConstFlags>("ConstFlags")
|
|
.value("CONST_FLAG_NONE",Yosys::RTLIL::CONST_FLAG_NONE)
|
|
.value("CONST_FLAG_STRING",Yosys::RTLIL::CONST_FLAG_STRING)
|
|
.value("CONST_FLAG_SIGNED",Yosys::RTLIL::CONST_FLAG_SIGNED)
|
|
.value("CONST_FLAG_REAL",Yosys::RTLIL::CONST_FLAG_REAL)
|
|
;
|
|
|
|
class_<MonitorWrap, boost::noncopyable>("Monitor")
|
|
.def("py_notify_module_add", &Monitor::py_notify_module_add, &MonitorWrap::default_py_notify_module_add)
|
|
.def("py_notify_module_del", &Monitor::py_notify_module_del, &MonitorWrap::default_py_notify_module_del)
|
|
.def("py_notify_connect_cell", &Monitor::py_notify_connect_cell, &MonitorWrap::default_py_notify_connect_cell)
|
|
.def("py_notify_connect_tuple", &Monitor::py_notify_connect_tuple, &MonitorWrap::default_py_notify_connect_tuple)
|
|
.def("py_notify_connect_list", &Monitor::py_notify_connect_list, &MonitorWrap::default_py_notify_connect_list)
|
|
.def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout)
|
|
;
|
|
|
|
class_<PassWrap, boost::noncopyable>("Pass", init<std::string, std::string>())
|
|
.def("py_execute", &PyPass::py_execute, &PassWrap::default_py_execute)
|
|
.def("py_help", &PyPass::py_help, &PassWrap::default_py_help)
|
|
;
|
|
|
|
class_<Initializer>("Initializer");
|
|
scope().attr("_hidden") = new Initializer();
|
|
|
|
class_<IdString>("IdString")
|
|
.def(init<std::string>())
|
|
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
|
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
|
.def("get_reference", &IdString::get_reference)
|
|
.def("put_reference", &IdString::put_reference)
|
|
.def("in_IdString", &IdString::in_IdString)
|
|
.def("in_std_string", &IdString::in_std_string)
|
|
;
|
|
|
|
class_<Const>("Const")
|
|
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
|
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
|
.def("as_int", &Const::as_int)
|
|
.def("from_string", &Const::from_string)
|
|
.def("extract", &Const::extract)
|
|
;
|
|
|
|
class_<CaseRule>("CaseRule")
|
|
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
|
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
|
;
|
|
|
|
class_<SwitchRule>("SwitchRule")
|
|
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
|
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
|
;
|
|
|
|
class_<SyncRule>("SyncRule")
|
|
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
|
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
|
;
|
|
|
|
class_<Process>("Process")
|
|
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
|
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
|
;
|
|
|
|
class_<SigChunk>("SigChunk")
|
|
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
|
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
|
.def("extract", &SigChunk::extract)
|
|
;
|
|
|
|
class_<SigBit>("SigBit")
|
|
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
|
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
|
;
|
|
|
|
class_<SigSpec>("SigSpec")
|
|
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
|
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
|
.def("replace_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec)
|
|
.def("replace_SigSpec_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec_SigSpec)
|
|
.def("replace_int_SigSpec", &SigSpec::replace_int_SigSpec)
|
|
.def("remove_SigSpec", &SigSpec::remove_SigSpec)
|
|
.def("remove_SigSpec_SigSpec", &SigSpec::remove_SigSpec_SigSpec)
|
|
.def("remove2_SigSpec_SigSpec", &SigSpec::remove2_SigSpec_SigSpec)
|
|
.def("remove_pool_SigBit", &SigSpec::remove_pool_SigBit)
|
|
.def("remove_pool_SigBit_SigSpec", &SigSpec::remove_pool_SigBit_SigSpec)
|
|
.def("remove2_pool_SigBit_SigSpec", &SigSpec::remove2_pool_SigBit_SigSpec)
|
|
.def("remove_int_int", &SigSpec::remove_int_int)
|
|
.def("extract_SigSpec_SigSpec", &SigSpec::extract_SigSpec_SigSpec)
|
|
.def("extract_pool_SigBit_SigSpec", &SigSpec::extract_pool_SigBit_SigSpec)
|
|
.def("extract_int_int", &SigSpec::extract_int_int)
|
|
.def("append", &SigSpec::append)
|
|
.def("append_bit", &SigSpec::append_bit)
|
|
.def("extend_u0", &SigSpec::extend_u0)
|
|
.def("repeat", &SigSpec::repeat)
|
|
.def("as_int", &SigSpec::as_int)
|
|
.def("match", &SigSpec::match)
|
|
.def("parse", &SigSpec::parse)
|
|
.def("parse_sel", &SigSpec::parse_sel)
|
|
.def("parse_rhs", &SigSpec::parse_rhs)
|
|
;
|
|
|
|
class_<Cell>("Cell", no_init)
|
|
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
|
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
|
.def("hasPort", &Cell::hasPort)
|
|
.def("unsetPort", &Cell::unsetPort)
|
|
.def("setPort", &Cell::setPort)
|
|
.def("input", &Cell::input)
|
|
.def("output", &Cell::output)
|
|
.def("hasParam", &Cell::hasParam)
|
|
.def("unsetParam", &Cell::unsetParam)
|
|
.def("setParam", &Cell::setParam)
|
|
.def("fixup_parameters", &Cell::fixup_parameters)
|
|
;
|
|
|
|
class_<Wire>("Wire", no_init)
|
|
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
|
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
|
;
|
|
|
|
class_<Memory>("Memory", no_init)
|
|
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
|
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
|
;
|
|
|
|
class_<Module>("Module")
|
|
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
|
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
|
.def("get_cells", &Module::get_cells)
|
|
.def("get_wires", &Module::get_wires)
|
|
.def("register_monitor", &Module::register_monitor)
|
|
.def("connect_SigSig", &Module::connect_SigSig)
|
|
.def("connect_SigSpec_SigSpec", &Module::connect_SigSpec_SigSpec)
|
|
.def("new_connections", &Module::new_connections)
|
|
.def("cloneInto", &Module::cloneInto)
|
|
.def("remove_pool_Wire", &Module::remove_pool_Wire)
|
|
.def("remove_Cell", &Module::remove_Cell)
|
|
.def("rename_Wire_IdString", &Module::rename_Wire_IdString)
|
|
.def("rename_Cell_IdString", &Module::rename_Cell_IdString)
|
|
.def("rename_IdString_IdString", &Module::rename_IdString_IdString)
|
|
.def("swap_names_Wire_Wire", &Module::swap_names_Wire_Wire)
|
|
.def("swap_names_Cell_Cell", &Module::swap_names_Cell_Cell)
|
|
.def("uniquify_IdString", &Module::uniquify_IdString)
|
|
.def("uniquify_IdString_int", &Module::uniquify_IdString_int)
|
|
.def("addWire_IdString_int", &Module::addWire_IdString_int)
|
|
.def("addWire_IdString_Wire", &Module::addWire_IdString_Wire)
|
|
.def("addCell_IdString_IdString", &Module::addCell_IdString_IdString)
|
|
.def("addCell_IdString_Cell", &Module::addCell_IdString_Cell)
|
|
.def("addNot", &Module::addNot)
|
|
.def("addPos", &Module::addPos)
|
|
.def("addNeg", &Module::addNeg)
|
|
.def("addAnd", &Module::addAnd)
|
|
.def("addOr", &Module::addOr)
|
|
.def("addXor", &Module::addXor)
|
|
.def("addXnor", &Module::addXnor)
|
|
.def("addReduceAnd", &Module::addReduceAnd)
|
|
.def("addReduceOr", &Module::addReduceOr)
|
|
.def("addReduceXor", &Module::addReduceXor)
|
|
.def("addReduceXnor", &Module::addReduceXnor)
|
|
.def("addReduceBool", &Module::addReduceBool)
|
|
.def("addShl", &Module::addShl)
|
|
.def("addShr", &Module::addShr)
|
|
.def("addSshl", &Module::addSshl)
|
|
.def("addSshr", &Module::addSshr)
|
|
.def("addShift", &Module::addShift)
|
|
.def("addShiftx", &Module::addShiftx)
|
|
.def("addLt", &Module::addLt)
|
|
.def("addLe", &Module::addLe)
|
|
.def("addEq", &Module::addEq)
|
|
.def("addNe", &Module::addNe)
|
|
.def("addEqx", &Module::addEqx)
|
|
.def("addNex", &Module::addNex)
|
|
.def("addGe", &Module::addGe)
|
|
.def("addGt", &Module::addGt)
|
|
.def("addAdd", &Module::addAdd)
|
|
.def("addSub", &Module::addSub)
|
|
.def("addMul", &Module::addMul)
|
|
.def("addDiv", &Module::addDiv)
|
|
.def("addMod", &Module::addMod)
|
|
.def("addPow", &Module::addPow)
|
|
.def("addLogicNot", &Module::addLogicNot)
|
|
.def("addLogicAnd", &Module::addLogicAnd)
|
|
.def("addLogicOr", &Module::addLogicOr)
|
|
.def("addMux", &Module::addMux)
|
|
.def("addPmux", &Module::addPmux)
|
|
.def("addSlice", &Module::addSlice)
|
|
.def("addConcat", &Module::addConcat)
|
|
.def("addLut", &Module::addLut)
|
|
.def("addTribuf", &Module::addTribuf)
|
|
.def("addAssert", &Module::addAssert)
|
|
.def("addAssume", &Module::addAssume)
|
|
.def("addLive", &Module::addLive)
|
|
.def("addFair", &Module::addFair)
|
|
.def("addCover", &Module::addCover)
|
|
.def("addEquiv", &Module::addEquiv)
|
|
.def("addSr", &Module::addSr)
|
|
.def("addFf", &Module::addFf)
|
|
.def("addDff", &Module::addDff)
|
|
.def("addDffe", &Module::addDffe)
|
|
.def("addDlatch", &Module::addDlatch)
|
|
.def("addBufGate", &Module::addBufGate)
|
|
.def("addNotGate", &Module::addNotGate)
|
|
.def("addAndGate", &Module::addAndGate)
|
|
.def("addNandGate", &Module::addNandGate)
|
|
.def("addOrGate", &Module::addOrGate)
|
|
.def("addNorGate", &Module::addNorGate)
|
|
.def("addXorGate", &Module::addXorGate)
|
|
.def("addXnorGate", &Module::addXnorGate)
|
|
.def("addAndnotGate", &Module::addAndnotGate)
|
|
.def("addOrnotGate", &Module::addOrnotGate)
|
|
.def("addMuxGate", &Module::addMuxGate)
|
|
.def("addAoi3Gate", &Module::addAoi3Gate)
|
|
.def("addOai3Gate", &Module::addOai3Gate)
|
|
.def("addAoi4Gate", &Module::addAoi4Gate)
|
|
.def("addOai4Gate", &Module::addOai4Gate)
|
|
.def("addFfGate", &Module::addFfGate)
|
|
.def("addDffGate", &Module::addDffGate)
|
|
.def("addDffeGate", &Module::addDffeGate)
|
|
.def("addDlatchGate", &Module::addDlatchGate)
|
|
.def("Not", &Module::Not)
|
|
.def("Pos", &Module::Pos)
|
|
.def("Neg", &Module::Neg)
|
|
.def("And", &Module::And)
|
|
.def("Or", &Module::Or)
|
|
.def("Xor", &Module::Xor)
|
|
.def("Xnor", &Module::Xnor)
|
|
.def("ReduceAnd", &Module::ReduceAnd)
|
|
.def("ReduceOr", &Module::ReduceOr)
|
|
.def("ReduceXor", &Module::ReduceXor)
|
|
.def("ReduceXnor", &Module::ReduceXnor)
|
|
.def("ReduceBool", &Module::ReduceBool)
|
|
.def("Shl", &Module::Shl)
|
|
.def("Shr", &Module::Shr)
|
|
.def("Sshl", &Module::Sshl)
|
|
.def("Sshr", &Module::Sshr)
|
|
.def("Shift", &Module::Shift)
|
|
.def("Shiftx", &Module::Shiftx)
|
|
.def("Lt", &Module::Lt)
|
|
.def("Le", &Module::Le)
|
|
.def("Eq", &Module::Eq)
|
|
.def("Ne", &Module::Ne)
|
|
.def("Eqx", &Module::Eqx)
|
|
.def("Nex", &Module::Nex)
|
|
.def("Ge", &Module::Ge)
|
|
.def("Gt", &Module::Gt)
|
|
.def("Add", &Module::Add)
|
|
.def("Sub", &Module::Sub)
|
|
.def("Mul", &Module::Mul)
|
|
.def("Div", &Module::Div)
|
|
.def("Mod", &Module::Mod)
|
|
.def("LogicNot", &Module::LogicNot)
|
|
.def("LogicAnd", &Module::LogicAnd)
|
|
.def("LogicOr", &Module::LogicOr)
|
|
.def("Mux", &Module::Mux)
|
|
.def("Pmux", &Module::Pmux)
|
|
.def("BufGate", &Module::BufGate)
|
|
.def("NotGate", &Module::NotGate)
|
|
.def("AndGate", &Module::AndGate)
|
|
.def("NandGate", &Module::NandGate)
|
|
.def("OrGate", &Module::OrGate)
|
|
.def("NorGate", &Module::NorGate)
|
|
.def("XorGate", &Module::XorGate)
|
|
.def("XnorGate", &Module::XnorGate)
|
|
.def("AndnotGate", &Module::AndnotGate)
|
|
.def("OrnotGate", &Module::OrnotGate)
|
|
.def("MuxGate", &Module::MuxGate)
|
|
.def("Aoi3Gate", &Module::Aoi3Gate)
|
|
.def("Oai3Gate", &Module::Oai3Gate)
|
|
.def("Aoi4Gate", &Module::Aoi4Gate)
|
|
.def("Oai4Gate", &Module::Oai4Gate)
|
|
.def("Anyconst", &Module::Anyconst)
|
|
.def("Anyseq", &Module::Anyseq)
|
|
.def("Allconst", &Module::Allconst)
|
|
.def("Allseq", &Module::Allseq)
|
|
.def("Initstate", &Module::Initstate)
|
|
;
|
|
|
|
class_<Design>("Design")
|
|
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
|
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
|
.def("get_modules", &Design::get_modules)
|
|
.def("run", &Design::run)
|
|
.def("register_monitor", &Design::register_monitor)
|
|
.def("module", &Design::module)
|
|
.def("has", &Design::has)
|
|
.def("add", &Design::add)
|
|
.def("addModule", &Design::addModule)
|
|
.def("remove", &Design::remove)
|
|
.def("rename", &Design::rename)
|
|
.def("scratchpad_unset", &Design::scratchpad_unset)
|
|
.def("scratchpad_set_int", &Design::scratchpad_set_int)
|
|
.def("scratchpad_set_bool", &Design::scratchpad_set_bool)
|
|
.def("scratchpad_set_string", &Design::scratchpad_set_string)
|
|
.def("scratchpad_get_int", &Design::scratchpad_get_int)
|
|
.def("scratchpad_get_bool", &Design::scratchpad_get_bool)
|
|
.def("scratchpad_get_string", &Design::scratchpad_get_string)
|
|
.def("selected_module_IdString", &Design::selected_module_IdString)
|
|
.def("selected_whole_module_IdString", &Design::selected_whole_module_IdString)
|
|
.def("selected_member", &Design::selected_member)
|
|
.def("selected_module_Module", &Design::selected_module_Module)
|
|
.def("selected_whole_module_Module", &Design::selected_whole_module_Module)
|
|
;
|
|
|
|
def("escape_id", escape_id);
|
|
def("unescape_id_std_string", unescape_id_std_string);
|
|
def("unescape_id_IdString", unescape_id_IdString);
|
|
def("const_not", const_not);
|
|
def("const_and", const_and);
|
|
def("const_or", const_or);
|
|
def("const_xor", const_xor);
|
|
def("const_xnor", const_xnor);
|
|
def("const_reduce_and", const_reduce_and);
|
|
def("const_reduce_or", const_reduce_or);
|
|
def("const_reduce_xor", const_reduce_xor);
|
|
def("const_reduce_xnor", const_reduce_xnor);
|
|
def("const_reduce_bool", const_reduce_bool);
|
|
def("const_logic_not", const_logic_not);
|
|
def("const_logic_and", const_logic_and);
|
|
def("const_logic_or", const_logic_or);
|
|
def("const_shl", const_shl);
|
|
def("const_shr", const_shr);
|
|
def("const_sshl", const_sshl);
|
|
def("const_sshr", const_sshr);
|
|
def("const_shift", const_shift);
|
|
def("const_shiftx", const_shiftx);
|
|
def("const_lt", const_lt);
|
|
def("const_le", const_le);
|
|
def("const_eq", const_eq);
|
|
def("const_ne", const_ne);
|
|
def("const_eqx", const_eqx);
|
|
def("const_nex", const_nex);
|
|
def("const_ge", const_ge);
|
|
def("const_gt", const_gt);
|
|
def("const_add", const_add);
|
|
def("const_sub", const_sub);
|
|
def("const_mul", const_mul);
|
|
def("const_div", const_div);
|
|
def("const_mod", const_mod);
|
|
def("const_pow", const_pow);
|
|
def("const_pos", const_pos);
|
|
def("const_neg", const_neg);
|
|
|
|
def("run",run);
|
|
def("log",log);
|
|
|
|
}
|
|
|
|
}
|
|
#endif
|