Clifford Wolf ec93680bd5 Renamed opt_share to opt_merge		2016-03-31 08:52:49 +02:00
..
tests	Initialization support for all iCE40 bram modes	2015-04-26 08:39:31 +02:00
.gitignore	Initialization support for all iCE40 bram modes	2015-04-26 08:39:31 +02:00
Makefile.inc	Added ice40_ffinit pass	2015-11-26 18:11:06 +01:00
arith_map.v	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
brams.txt	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
brams_init.py	Switched to Python 3	2015-08-22 09:59:33 +02:00
brams_map.v	Fixed WE/RE usage in iCE40 BRAM mapping	2015-11-24 10:51:34 +01:00
cells_map.v	improved ice40 dff cell mapping	2015-04-16 11:30:56 +02:00
cells_sim.v	Work around DDR dout sim glitches in ice40 SB_IO sim model	2016-02-07 11:19:48 +01:00
ice40_ffinit.cc	Bugfix in ice40_ffinit	2015-12-22 12:18:06 +01:00
ice40_ffssr.cc	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
ice40_opt.cc	Renamed opt_share to opt_merge	2016-03-31 08:52:49 +02:00
synth_ice40.cc	Renamed opt_const to opt_expr	2016-03-31 08:46:56 +02:00