mirror of https://github.com/YosysHQ/yosys.git
421 lines
11 KiB
C++
421 lines
11 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "blifparse.h"
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YOSYS_NAMESPACE_BEGIN
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static bool read_next_line(char *&buffer, size_t &buffer_size, int &line_count, std::istream &f)
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{
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int buffer_len = 0;
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buffer[0] = 0;
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while (1)
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{
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buffer_len += strlen(buffer + buffer_len);
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while (buffer_len > 0 && (buffer[buffer_len-1] == ' ' || buffer[buffer_len-1] == '\t' ||
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buffer[buffer_len-1] == '\r' || buffer[buffer_len-1] == '\n'))
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buffer[--buffer_len] = 0;
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if (buffer_size-buffer_len < 4096) {
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buffer_size *= 2;
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buffer = (char*)realloc(buffer, buffer_size);
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}
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if (buffer_len == 0 || buffer[buffer_len-1] == '\\') {
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if (buffer_len > 0 && buffer[buffer_len-1] == '\\')
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buffer[--buffer_len] = 0;
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line_count++;
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if (!f.getline(buffer+buffer_len, buffer_size-buffer_len))
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return false;
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} else
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return true;
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}
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}
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void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bool run_clean)
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{
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RTLIL::Module *module = nullptr;
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RTLIL::Const *lutptr = NULL;
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RTLIL::State lut_default_state = RTLIL::State::Sx;
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int blif_maxnum = 0;
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auto blif_wire = [&](const std::string &wire_name) -> Wire*
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{
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if (wire_name[0] == '$')
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{
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for (int i = 0; i+1 < GetSize(wire_name); i++)
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{
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if (wire_name[i] != '$')
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continue;
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int len = 0;
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while (i+len+1 < GetSize(wire_name) && '0' <= wire_name[i+len+1] && wire_name[i+len+1] <= '9')
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len++;
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if (len > 0) {
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string num_str = wire_name.substr(i+1, len);
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int num = atoi(num_str.c_str()) & 0x0fffffff;
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blif_maxnum = std::max(blif_maxnum, num);
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}
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}
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}
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IdString wire_id = RTLIL::escape_id(wire_name);
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Wire *wire = module->wire(wire_id);
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if (wire == nullptr)
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wire = module->addWire(wire_id);
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return wire;
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};
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dict<RTLIL::IdString, RTLIL::Const> *obj_attributes = nullptr;
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dict<RTLIL::IdString, RTLIL::Const> *obj_parameters = nullptr;
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size_t buffer_size = 4096;
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char *buffer = (char*)malloc(buffer_size);
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int line_count = 0;
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while (1)
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{
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if (!read_next_line(buffer, buffer_size, line_count, f)) {
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if (module != nullptr)
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goto error;
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free(buffer);
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return;
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}
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continue_without_read:
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if (buffer[0] == '#')
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continue;
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if (buffer[0] == '.')
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{
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if (lutptr) {
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for (auto &bit : lutptr->bits)
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if (bit == RTLIL::State::Sx)
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bit = lut_default_state;
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lutptr = NULL;
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lut_default_state = RTLIL::State::Sx;
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}
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char *cmd = strtok(buffer, " \t\r\n");
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if (!strcmp(cmd, ".model")) {
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if (module != nullptr)
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goto error;
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module = new RTLIL::Module;
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module->name = RTLIL::escape_id(strtok(NULL, " \t\r\n"));
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obj_attributes = &module->attributes;
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obj_parameters = nullptr;
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if (design->module(module->name))
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log_error("Duplicate definition of module %s in line %d!\n", log_id(module->name), line_count);
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design->add(module);
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continue;
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}
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if (module == nullptr)
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goto error;
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if (!strcmp(cmd, ".end"))
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{
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module->fixup_ports();
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if (run_clean)
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{
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Const buffer_lut(vector<RTLIL::State>({State::S0, State::S1}));
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vector<Cell*> remove_cells;
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for (auto cell : module->cells())
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if (cell->type == "$lut" && cell->getParam("\\LUT") == buffer_lut) {
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module->connect(cell->getPort("\\Y"), cell->getPort("\\A"));
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remove_cells.push_back(cell);
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}
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for (auto cell : remove_cells)
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module->remove(cell);
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Wire *true_wire = module->wire("$true");
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Wire *false_wire = module->wire("$false");
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Wire *undef_wire = module->wire("$undef");
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if (true_wire != nullptr)
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module->rename(true_wire, stringf("$true$%d", ++blif_maxnum));
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if (false_wire != nullptr)
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module->rename(false_wire, stringf("$false$%d", ++blif_maxnum));
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if (undef_wire != nullptr)
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module->rename(undef_wire, stringf("$undef$%d", ++blif_maxnum));
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autoidx = std::max(autoidx, blif_maxnum+1);
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blif_maxnum = 0;
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}
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module = nullptr;
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obj_attributes = nullptr;
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obj_parameters = nullptr;
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continue;
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}
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if (!strcmp(cmd, ".inputs") || !strcmp(cmd, ".outputs")) {
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char *p;
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while ((p = strtok(NULL, " \t\r\n")) != NULL) {
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RTLIL::IdString wire_name(stringf("\\%s", p));
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RTLIL::Wire *wire = module->wire(wire_name);
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if (wire == nullptr)
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wire = module->addWire(wire_name);
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if (!strcmp(cmd, ".inputs"))
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wire->port_input = true;
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else
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wire->port_output = true;
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}
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obj_attributes = nullptr;
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obj_parameters = nullptr;
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continue;
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}
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if (!strcmp(cmd, ".attr") || !strcmp(cmd, ".param")) {
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char *n = strtok(NULL, " \t\r\n");
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char *v = strtok(NULL, "\r\n");
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IdString id_n = RTLIL::escape_id(n);
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Const const_v;
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if (v[0] == '"') {
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std::string str(v+1);
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if (str.back() == '"')
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str.resize(str.size()-1);
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const_v = Const(str);
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} else {
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int n = strlen(v);
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const_v.bits.resize(n);
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for (int i = 0; i < n; i++)
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const_v.bits[i] = v[n-i-1] != '0' ? State::S1 : State::S0;
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}
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if (!strcmp(cmd, ".attr")) {
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if (obj_attributes == nullptr)
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goto error;
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(*obj_attributes)[id_n] = const_v;
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} else {
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if (obj_parameters == nullptr)
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goto error;
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(*obj_parameters)[id_n] = const_v;
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}
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continue;
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}
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if (!strcmp(cmd, ".latch"))
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{
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char *d = strtok(NULL, " \t\r\n");
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char *q = strtok(NULL, " \t\r\n");
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char *edge = strtok(NULL, " \t\r\n");
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char *clock = strtok(NULL, " \t\r\n");
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char *init = strtok(NULL, " \t\r\n");
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RTLIL::Cell *cell = nullptr;
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if (clock == nullptr && edge != nullptr) {
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init = edge;
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edge = nullptr;
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}
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if (init != nullptr && (init[0] == '0' || init[0] == '1'))
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blif_wire(d)->attributes["\\init"] = Const(init[0] == '1' ? 1 : 0, 1);
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if (clock == nullptr)
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goto no_latch_clock;
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if (!strcmp(edge, "re"))
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cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
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else if (!strcmp(edge, "fe"))
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cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
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else {
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no_latch_clock:
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cell = module->addCell(NEW_ID, dff_name);
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cell->setPort("\\D", blif_wire(d));
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cell->setPort("\\Q", blif_wire(q));
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}
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obj_attributes = &cell->attributes;
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obj_parameters = &cell->parameters;
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continue;
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}
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if (!strcmp(cmd, ".gate") || !strcmp(cmd, ".subckt"))
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{
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char *p = strtok(NULL, " \t\r\n");
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if (p == NULL)
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goto error;
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IdString celltype = RTLIL::escape_id(p);
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RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
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while ((p = strtok(NULL, " \t\r\n")) != NULL) {
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char *q = strchr(p, '=');
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if (q == NULL || !q[0])
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goto error;
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*(q++) = 0;
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cell->setPort(RTLIL::escape_id(p), *q ? blif_wire(q) : SigSpec());
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}
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obj_attributes = &cell->attributes;
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obj_parameters = &cell->parameters;
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continue;
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}
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obj_attributes = nullptr;
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obj_parameters = nullptr;
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if (!strcmp(cmd, ".barbuf"))
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{
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char *p = strtok(NULL, " \t\r\n");
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if (p == NULL)
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goto error;
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char *q = strtok(NULL, " \t\r\n");
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if (q == NULL)
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goto error;
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module->connect(blif_wire(q), blif_wire(p));
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continue;
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}
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if (!strcmp(cmd, ".names"))
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{
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char *p;
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RTLIL::SigSpec input_sig, output_sig;
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while ((p = strtok(NULL, " \t\r\n")) != NULL)
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input_sig.append(blif_wire(p));
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output_sig = input_sig.extract(input_sig.size()-1, 1);
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input_sig = input_sig.extract(0, input_sig.size()-1);
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if (input_sig.size() == 0)
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{
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RTLIL::State state = RTLIL::State::Sa;
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while (1) {
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if (!read_next_line(buffer, buffer_size, line_count, f))
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goto error;
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for (int i = 0; buffer[i]; i++) {
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if (buffer[i] == ' ' || buffer[i] == '\t')
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continue;
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if (i == 0 && buffer[i] == '.')
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goto finished_parsing_constval;
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if (buffer[i] == '0') {
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if (state == RTLIL::State::S1)
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goto error;
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state = RTLIL::State::S0;
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continue;
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}
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if (buffer[i] == '1') {
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if (state == RTLIL::State::S0)
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goto error;
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state = RTLIL::State::S1;
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continue;
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}
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goto error;
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}
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}
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finished_parsing_constval:
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if (state == RTLIL::State::Sa)
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state = RTLIL::State::S0;
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if (output_sig.as_wire()->name == "$undef")
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state = RTLIL::State::Sx;
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module->connect(RTLIL::SigSig(output_sig, state));
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goto continue_without_read;
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}
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RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
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cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
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cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
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cell->setPort("\\A", input_sig);
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cell->setPort("\\Y", output_sig);
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lutptr = &cell->parameters.at("\\LUT");
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lut_default_state = RTLIL::State::Sx;
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continue;
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}
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goto error;
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}
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if (lutptr == NULL)
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goto error;
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char *input = strtok(buffer, " \t\r\n");
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char *output = strtok(NULL, " \t\r\n");
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if (input == NULL || output == NULL || (strcmp(output, "0") && strcmp(output, "1")))
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goto error;
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int input_len = strlen(input);
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if (input_len > 8)
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goto error;
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for (int i = 0; i < (1 << input_len); i++) {
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for (int j = 0; j < input_len; j++) {
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char c1 = input[j];
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if (c1 != '-') {
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char c2 = (i & (1 << j)) != 0 ? '1' : '0';
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if (c1 != c2)
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goto try_next_value;
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}
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}
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lutptr->bits.at(i) = !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1;
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try_next_value:;
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}
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lut_default_state = !strcmp(output, "0") ? RTLIL::State::S1 : RTLIL::State::S0;
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}
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error:
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log_error("Syntax error in line %d!\n", line_count);
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}
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struct BlifFrontend : public Frontend {
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BlifFrontend() : Frontend("blif", "read BLIF file") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" read_blif [filename]\n");
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log("\n");
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log("Load modules from a BLIF file into the current design.\n");
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log("\n");
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}
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virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing BLIF frontend.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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// if (arg == "-lib") {
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// flag_lib = true;
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// continue;
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// }
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break;
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}
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extra_args(f, filename, args, argidx);
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parse_blif(design, *f, "\\DFF", true);
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}
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} BlifFrontend;
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YOSYS_NAMESPACE_END
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