mirror of https://github.com/YosysHQ/yosys.git
143 lines
3.9 KiB
Verilog
143 lines
3.9 KiB
Verilog
/* Semi Dual Port (SDP) memory have the following configurations:
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* Memory Config RAM(BIT) Port Mode Memory Depth Data Depth
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* ----------------|---------| ----------|--------------|------------|
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* B-SRAM_16K_SD1 16K 16Kx1 16,384 1
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* B-SRAM_8K_SD2 16K 8Kx2 8,192 2
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* B-SRAM_4K_SD4 16K 4Kx2 4,096 4
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*/
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module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 10;
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parameter CFG_DBITS = 16;
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parameter CFG_ENABLE_A = 1;
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parameter [16383:0] INIT = 16384'hx;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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input CLK2;
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input CLK3;
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input [CFG_ABITS-1:0] A1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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input [CFG_ENABLE_A-1:0] A1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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output [CFG_DBITS-1:0] B1DATA;
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input B1EN;
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wire [31-CFG_DBITS:0] open;
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generate if (CFG_DBITS == 1) begin
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SDP #(
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`include "bram_init_16.vh"
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.READ_MODE(0),
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.BIT_WIDTH_0(1),
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.BIT_WIDTH_1(1),
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.BLK_SEL(3'b000),
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.RESET_MODE("SYNC")
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) _TECHMAP_REPLACE_ (
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.CLKA(CLK2), .CLKB(CLK3),
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.WREA(A1EN), .OCE(1'b0), .CEA(1'b1),
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.WREB(1'b0), .CEB(B1EN),
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.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
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.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
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.DO({open, B1DATA}),
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.ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
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.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
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);
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end else if (CFG_DBITS == 2) begin
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SDP #(
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`include "bram_init_16.vh"
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.READ_MODE(0),
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.BIT_WIDTH_0(2),
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.BIT_WIDTH_1(2),
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.BLK_SEL(3'b000),
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.RESET_MODE("SYNC")
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) _TECHMAP_REPLACE_ (
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.CLKA(CLK2), .CLKB(CLK3),
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.WREA(A1EN), .OCE(1'b0), .CEA(1'b1),
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.WREB(1'b0), .CEB(B1EN),
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.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
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.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
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.DO({open, B1DATA}),
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.ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
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.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
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);
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end else if (CFG_DBITS <= 4) begin
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SDP #(
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`include "bram_init_16.vh"
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.READ_MODE(0),
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.BIT_WIDTH_0(4),
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.BIT_WIDTH_1(4),
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.BLK_SEL(3'b000),
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.RESET_MODE("SYNC")
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) _TECHMAP_REPLACE_ (
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.CLKA(CLK2), .CLKB(CLK3),
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.WREA(A1EN), .OCE(1'b0),
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.WREB(1'b0), .CEB(B1EN), .CEA(1'b1),
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.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
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.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
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.DO({open, B1DATA}),
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.ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
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.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
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);
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end else if (CFG_DBITS <= 8) begin
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SDP #(
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`include "bram_init_16.vh"
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.READ_MODE(0),
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.BIT_WIDTH_0(8),
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.BIT_WIDTH_1(8),
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.BLK_SEL(3'b000),
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.RESET_MODE("SYNC")
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) _TECHMAP_REPLACE_ (
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.CLKA(CLK2), .CLKB(CLK3),
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.WREA(A1EN), .OCE(1'b0), .CEA(1'b1),
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.WREB(1'b0), .CEB(B1EN),
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.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
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.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
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.DO({open, B1DATA}),
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.ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
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.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
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);
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end else if (CFG_DBITS <= 16) begin
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SDP #(
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`include "bram_init_16.vh"
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.READ_MODE(0),
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.BIT_WIDTH_0(16),
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.BIT_WIDTH_1(16),
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.BLK_SEL(3'b000),
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.RESET_MODE("SYNC")
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) _TECHMAP_REPLACE_ (
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.CLKA(CLK2), .CLKB(CLK3),
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.WREA(|A1EN), .OCE(1'b0),
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.WREB(1'b0), .CEB(B1EN), .CEA(1'b1),
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.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
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.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
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.DO({open, B1DATA}),
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.ADA({A1ADDR, {(12-CFG_ABITS){1'b0}}, A1EN}),
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.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
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);
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end else if (CFG_DBITS <= 32) begin
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SDP #(
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`include "bram_init_16.vh"
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.READ_MODE(0),
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.BIT_WIDTH_0(32),
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.BIT_WIDTH_1(32),
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.BLK_SEL(3'b000),
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.RESET_MODE("SYNC")
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) _TECHMAP_REPLACE_ (
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.CLKA(CLK2), .CLKB(CLK3),
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.WREA(|A1EN), .OCE(1'b0),
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.WREB(1'b0), .CEB(B1EN), .CEA(1'b1),
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.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
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.DI(A1DATA),
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.DO(B1DATA),
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.ADA({A1ADDR, {(10-CFG_ABITS){1'b0}}, A1EN}),
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.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
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);
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end else begin
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wire TECHMAP_FAIL = 1'b1;
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end endgenerate
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endmodule
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