mirror of https://github.com/YosysHQ/yosys.git
600 lines
26 KiB
TeX
600 lines
26 KiB
TeX
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\chapter{Internal Cell Library}
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\label{chapter:celllib}
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Most of the passes in Yosys operate on netlists, i.e.~they only care about the RTLIL::Wire and RTLIL::Cell
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objects in an RTLIL::Module. This chapter discusses the cell types used by Yosys to represent a behavioural
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design internally.
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This chapter is split in two parts. In the first part the internal RTL cells are covered. These cells
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are used to represent the design on a coarse grain level. Like in the original HDL code on this level the
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cells operate on vectors of signals and complex cells like adders exist. In the second part the internal
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gate cells are covered. These cells are used to represent the design on a fine-grain gate-level. All cells
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from this category operate on single bit signals.
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\section{RTL Cells}
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Most of the RTL cells closely resemble the operators available in HDLs such as
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Verilog or VHDL. Therefore Verilog operators are used in the following sections
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to define the behaviour of the RTL cells.
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Note that all RTL cells have parameters indicating the size of inputs and outputs. When
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passes modify RTL cells they must always keep the values of these parameters in sync with
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the size of the signals connected to the inputs and outputs.
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Simulation models for the RTL cells can be found in the file {\tt techlibs/common/simlib.v} in the Yosys
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source tree.
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\subsection{Unary Operators}
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All unary RTL cells have one input port \B{A} and one output port \B{Y}. They also
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have the following parameters:
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\begin{itemize}
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\item \B{A\_SIGNED} \\
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Set to a non-zero value if the input \B{A} is signed and therefore should be sign-extended
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when needed.
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\item \B{A\_WIDTH} \\
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The width of the input port \B{A}.
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\item \B{Y\_WIDTH} \\
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The width of the output port \B{Y}.
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\end{itemize}
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Table~\ref{tab:CellLib_unary} lists all cells for unary RTL operators.
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\begin{table}[t!]
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\hfil
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\begin{tabular}{ll}
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Verilog & Cell Type \\
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\hline
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\lstinline[language=Verilog]; Y = ~A ; & {\tt \$not} \\
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\lstinline[language=Verilog]; Y = +A ; & {\tt \$pos} \\
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\lstinline[language=Verilog]; Y = -A ; & {\tt \$neg} \\
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\hline
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\lstinline[language=Verilog]; Y = &A ; & {\tt \$reduce\_and} \\
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\lstinline[language=Verilog]; Y = |A ; & {\tt \$reduce\_or} \\
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\lstinline[language=Verilog]; Y = ^A ; & {\tt \$reduce\_xor} \\
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\lstinline[language=Verilog]; Y = ~^A ; & {\tt \$reduce\_xnor} \\
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\hline
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\lstinline[language=Verilog]; Y = |A ; & {\tt \$reduce\_bool} \\
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\lstinline[language=Verilog]; Y = !A ; & {\tt \$logic\_not}
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\end{tabular}
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\caption{Cell types for unary operators with their corresponding Verilog expressions.}
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\label{tab:CellLib_unary}
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\end{table}
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For the unary cells that output a logical value ({\tt \$reduce\_and}, {\tt \$reduce\_or},
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{\tt \$reduce\_xor}, {\tt \$reduce\_xnor}, {\tt \$reduce\_bool}, {\tt \$logic\_not}),
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when the \B{Y\_WIDTH} parameter is greater than 1, the output is zero-extended,
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and only the least significant bit varies.
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Note that {\tt \$reduce\_or} and {\tt \$reduce\_bool} actually represent the same
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logic function. But the HDL frontends generate them in different situations. A
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{\tt \$reduce\_or} cell is generated when the prefix {\tt |} operator is being used. A
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{\tt \$reduce\_bool} cell is generated when a bit vector is used as a condition in
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an {\tt if}-statement or {\tt ?:}-expression.
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\subsection{Binary Operators}
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All binary RTL cells have two input ports \B{A} and \B{B} and one output port \B{Y}. They
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also have the following parameters:
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\begin{itemize}
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\item \B{A\_SIGNED} \\
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Set to a non-zero value if the input \B{A} is signed and therefore should be sign-extended
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when needed.
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\item \B{A\_WIDTH} \\
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The width of the input port \B{A}.
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\item \B{B\_SIGNED} \\
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Set to a non-zero value if the input \B{B} is signed and therefore should be sign-extended
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when needed.
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\item \B{B\_WIDTH} \\
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The width of the input port \B{B}.
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\item \B{Y\_WIDTH} \\
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The width of the output port \B{Y}.
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\end{itemize}
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Table~\ref{tab:CellLib_binary} lists all cells for binary RTL operators.
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\begin{table}[t!]
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\hfil
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\begin{tabular}[t]{ll}
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Verilog & Cell Type \\
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\hline
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\lstinline[language=Verilog]; Y = A & B; & {\tt \$and} \\
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\lstinline[language=Verilog]; Y = A | B; & {\tt \$or} \\
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\lstinline[language=Verilog]; Y = A ^ B; & {\tt \$xor} \\
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\lstinline[language=Verilog]; Y = A ~^ B; & {\tt \$xnor} \\
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\hline
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\lstinline[language=Verilog]; Y = A << B; & {\tt \$shl} \\
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\lstinline[language=Verilog]; Y = A >> B; & {\tt \$shr} \\
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\lstinline[language=Verilog]; Y = A <<< B; & {\tt \$sshl} \\
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\lstinline[language=Verilog]; Y = A >>> B; & {\tt \$sshr} \\
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\hline
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\lstinline[language=Verilog]; Y = A && B; & {\tt \$logic\_and} \\
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\lstinline[language=Verilog]; Y = A || B; & {\tt \$logic\_or} \\
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\hline
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\lstinline[language=Verilog]; Y = A === B; & {\tt \$eqx} \\
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\lstinline[language=Verilog]; Y = A !== B; & {\tt \$nex} \\
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\end{tabular}
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\hfil
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\begin{tabular}[t]{ll}
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Verilog & Cell Type \\
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\hline
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\lstinline[language=Verilog]; Y = A < B; & {\tt \$lt} \\
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\lstinline[language=Verilog]; Y = A <= B; & {\tt \$le} \\
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\lstinline[language=Verilog]; Y = A == B; & {\tt \$eq} \\
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\lstinline[language=Verilog]; Y = A != B; & {\tt \$ne} \\
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\lstinline[language=Verilog]; Y = A >= B; & {\tt \$ge} \\
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\lstinline[language=Verilog]; Y = A > B; & {\tt \$gt} \\
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\hline
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\lstinline[language=Verilog]; Y = A + B; & {\tt \$add} \\
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\lstinline[language=Verilog]; Y = A - B; & {\tt \$sub} \\
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\lstinline[language=Verilog]; Y = A * B; & {\tt \$mul} \\
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\lstinline[language=Verilog]; Y = A / B; & {\tt \$div} \\
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\lstinline[language=Verilog]; Y = A % B; & {\tt \$mod} \\
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\lstinline[language=Verilog]; Y = A ** B; & {\tt \$pow} \\
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\end{tabular}
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\caption{Cell types for binary operators with their corresponding Verilog expressions.}
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\label{tab:CellLib_binary}
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\end{table}
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The {\tt \$shl} and {\tt \$shr} cells implement logical shifts, whereas the {\tt \$sshl} and
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{\tt \$sshr} cells implement arithmetic shifts. The {\tt \$shl} and {\tt \$sshl} cells implement
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the same operation. All four of these cells interpret the second operand as unsigned, and require
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\B{B\_SIGNED} to be zero.
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Two additional shift operator cells are available that do not directly correspond to any operator
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in Verilog, {\tt \$shift} and {\tt \$shiftx}. The {\tt \$shift} cell performs a right logical shift
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if the second operand is positive (or unsigned), and a left logical shift if it is negative.
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The {\tt \$shiftx} cell performs the same operation as the {\tt \$shift} cell, but the vacated bit
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positions are filled with undef (x) bits, and corresponds to the Verilog indexed part-select expression.
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For the binary cells that output a logical value ({\tt \$logic\_and}, {\tt \$logic\_or},
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{\tt \$eqx}, {\tt \$nex}, {\tt \$lt}, {\tt \$le}, {\tt \$eq}, {\tt \$ne}, {\tt \$ge},
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{\tt \$gt}), when the \B{Y\_WIDTH} parameter is greater than 1, the output is zero-extended,
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and only the least significant bit varies.
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\subsection{Multiplexers}
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Multiplexers are generated by the Verilog HDL frontend for {\tt
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?:}-expressions. Multiplexers are also generated by the {\tt proc} pass to map the decision trees
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from RTLIL::Process objects to logic.
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The simplest multiplexer cell type is {\tt \$mux}. Cells of this type have a \B{WIDTH} parameter
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and data inputs \B{A} and \B{B} and a data output \B{Y}, all of the specified width. This cell also
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has a single bit control input \B{S}. If \B{S} is 0 the value from the \B{A} input is sent to
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the output, if it is 1 the value from the \B{B} input is sent to the output. So the {\tt \$mux}
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cell implements the function \lstinline[language=Verilog]; Y = S ? B : A;.
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The {\tt \$pmux} cell is used to multiplex between many inputs using a one-hot select signal. Cells
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of this type have a \B{WIDTH} and a \B{S\_WIDTH} parameter and inputs \B{A}, \B{B}, and \B{S} and
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an output \B{Y}. The \B{S} input is \B{S\_WIDTH} bits wide. The \B{A} input and the output are both
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\B{WIDTH} bits wide and the \B{B} input is \B{WIDTH}*\B{S\_WIDTH} bits wide. When all bits of
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\B{S} are zero, the value from \B{A} input is sent to the output. If the $n$'th bit from \B{S} is
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set, the value $n$'th \B{WIDTH} bits wide slice of the \B{B} input is sent to the output. When more
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than one bit from \B{S} is set the output is undefined. Cells of this type are used to model
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``parallel cases'' (defined by using the {\tt parallel\_case} attribute or detected by
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an optimization).
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The {\tt \$tribuf} cell is used to implement tristate logic. Cells of this type have a \B{WIDTH}
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parameter and inputs \B{A} and \B{EN} and an output \B{Y}. The \B{A} input and \B{Y} output are
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\B{WIDTH} bits wide, and the \B{EN} input is one bit wide. When \B{EN} is 0, the output \B{Y}
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is not driven. When \B{EN} is 1, the value from \B{A} input is sent to the \B{Y} output. Therefore,
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the {\tt \$tribuf} cell implements the function \lstinline[language=Verilog]; Y = EN ? A : 'bz;.
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Behavioural code with cascaded {\tt if-then-else}- and {\tt case}-statements
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usually results in trees of multiplexer cells. Many passes (from various
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optimizations to FSM extraction) heavily depend on these multiplexer trees to
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understand dependencies between signals. Therefore optimizations should not
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break these multiplexer trees (e.g.~by replacing a multiplexer between a
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calculated signal and a constant zero with an {\tt \$and} gate).
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\subsection{Registers}
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D-type flip-flops are represented by {\tt \$dff} cells. These cells have a clock port \B{CLK},
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an input port \B{D} and an output port \B{Q}. The following parameters are available for {\tt \$dff}
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cells:
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\begin{itemize}
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\item \B{WIDTH} \\
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The width of input \B{D} and output \B{Q}.
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\item \B{CLK\_POLARITY} \\
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Clock is active on the positive edge if this parameter has the value {\tt 1'b1} and on the negative
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edge if this parameter is {\tt 1'b0}.
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\end{itemize}
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D-type flip-flops with enable are represented by {\tt \$dffe} cells. As the {\tt \$dff}
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cells they have \B{CLK}, \B{D} and \B{Q} ports. In addition they also have a single-bit \B{EN}
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input port for the enable pin and the following parameter:
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\begin{itemize}
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\item \B{EN\_POLARITY} \\
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The enable input is active-high if this parameter has the value {\tt 1'b1} and active-low
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if this parameter is {\tt 1'b0}.
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\end{itemize}
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D-type flip-flops with asynchronous reset are represented by {\tt \$adff} cells. As the {\tt \$dff}
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cells they have \B{CLK}, \B{D} and \B{Q} ports. In addition they also have a single-bit \B{ARST}
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input port for the reset pin and the following additional two parameters:
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\begin{itemize}
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\item \B{ARST\_POLARITY} \\
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The asynchronous reset is active-high if this parameter has the value {\tt 1'b1} and active-low
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if this parameter is {\tt 1'b0}.
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\item \B{ARST\_VALUE} \\
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The state of \B{Q} will be set to this value when the reset is active.
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\end{itemize}
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Note that the {\tt \$adff} cell can only be used when the reset value is constant.
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\begin{sloppypar}
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Usually these cells are generated by the {\tt proc} pass using the information
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in the designs RTLIL::Process objects.
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\end{sloppypar}
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D-type flip-flops with asynchronous set and reset are represented by {\tt \$dffsr} cells.
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As the {\tt \$dff} cells they have \B{CLK}, \B{D} and \B{Q} ports. In addition they also have
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a single-bit \B{SET} input port for the set pin, a single-bit \B{CLR} input port for the reset pin,
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and the following two parameters:
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\begin{itemize}
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\item \B{SET\_POLARITY} \\
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The set input is active-high if this parameter has the value {\tt 1'b1} and active-low
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if this parameter is {\tt 1'b0}.
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\item \B{CLR\_POLARITY} \\
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The reset input is active-high if this parameter has the value {\tt 1'b1} and active-low
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if this parameter is {\tt 1'b0}.
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\end{itemize}
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When both the set and reset inputs of a {\tt \$dffsr} cell are active, the reset input takes
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precedence.
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\begin{fixme}
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Add information about {\tt \$sr} cells (set-reset flip-flops), {\tt \$dlatch} cells (d-type latches),
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and {\tt \$dlatchsr} cells (d-type latches with set/reset).
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\end{fixme}
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\subsection{Memories}
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\label{sec:memcells}
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Memories are either represented using RTLIL::Memory objects, {\tt \$memrd}, {\tt \$memwr}, and {\tt \$meminit}
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cells, or by {\tt \$mem} cells alone.
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In the first alternative the RTLIL::Memory objects hold the general metadata for the memory (bit width,
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size in number of words, etc.) and for each port a {\tt \$memrd} (read port) or {\tt \$memwr} (write port)
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cell is created. Having individual cells for read and write ports has the advantage that they can be
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consolidated using resource sharing passes. In some cases this drastically reduces the number of required
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ports on the memory cell. In this alternative, memory initialization data is represented by {\tt \$meminit} cells,
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which allow delaying constant folding for initialization addresses and data until after the frontend finishes.
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The {\tt \$memrd} cells have a clock input \B{CLK}, an enable input \B{EN}, an
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address input \B{ADDR}, and a data output \B{DATA}. They also have the
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following parameters:
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\begin{itemize}
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\item \B{MEMID} \\
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The name of the RTLIL::Memory object that is associated with this read port.
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\item \B{ABITS} \\
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The number of address bits (width of the \B{ADDR} input port).
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\item \B{WIDTH} \\
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The number of data bits (width of the \B{DATA} output port).
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\item \B{CLK\_ENABLE} \\
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When this parameter is non-zero, the clock is used. Otherwise this read port is asynchronous and
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the \B{CLK} input is not used.
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\item \B{CLK\_POLARITY} \\
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Clock is active on the positive edge if this parameter has the value {\tt 1'b1} and on the negative
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edge if this parameter is {\tt 1'b0}.
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\item \B{TRANSPARENT} \\
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If this parameter is set to {\tt 1'b1}, a read and write to the same address in the same cycle will
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return the new value. Otherwise the old value is returned.
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\end{itemize}
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The {\tt \$memwr} cells have a clock input \B{CLK}, an enable input \B{EN} (one
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enable bit for each data bit), an address input \B{ADDR} and a data input
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\B{DATA}. They also have the following parameters:
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\begin{itemize}
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\item \B{MEMID} \\
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The name of the RTLIL::Memory object that is associated with this write port.
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\item \B{ABITS} \\
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The number of address bits (width of the \B{ADDR} input port).
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\item \B{WIDTH} \\
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The number of data bits (width of the \B{DATA} output port).
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\item \B{CLK\_ENABLE} \\
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When this parameter is non-zero, the clock is used. Otherwise this write port is asynchronous and
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the \B{CLK} input is not used.
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\item \B{CLK\_POLARITY} \\
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Clock is active on positive edge if this parameter has the value {\tt 1'b1} and on the negative
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edge if this parameter is {\tt 1'b0}.
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\item \B{PRIORITY} \\
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The cell with the higher integer value in this parameter wins a write conflict.
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\end{itemize}
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The {\tt \$meminit} cells have an address input \B{ADDR} and a data input \B{DATA}, with the width
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of the \B{DATA} port equal to \B{WIDTH} parameter times \B{WORDS} parameter. Both of the inputs
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must resolve to a constant for synthesis to succeed.
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\begin{itemize}
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\item \B{MEMID} \\
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The name of the RTLIL::Memory object that is associated with this initialization cell.
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\item \B{ABITS} \\
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The number of address bits (width of the \B{ADDR} input port).
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\item \B{WIDTH} \\
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The number of data bits per memory location.
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\item \B{WORDS} \\
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The number of consecutive memory locations initialized by this cell.
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\item \B{PRIORITY} \\
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The cell with the higher integer value in this parameter wins an initialization conflict.
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\end{itemize}
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The HDL frontend models a memory using RTLIL::Memory objects and asynchronous
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{\tt \$memrd} and {\tt \$memwr} cells. The {\tt memory} pass (i.e.~its various sub-passes) migrates
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{\tt \$dff} cells into the {\tt \$memrd} and {\tt \$memwr} cells making them synchronous, then
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converts them to a single {\tt \$mem} cell and (optionally) maps this cell type
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to {\tt \$dff} cells for the individual words and multiplexer-based address decoders for the read and
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write interfaces. When the last step is disabled or not possible, a {\tt \$mem} cell is left in the design.
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The {\tt \$mem} cell provides the following parameters:
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\begin{itemize}
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\item \B{MEMID} \\
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The name of the original RTLIL::Memory object that became this {\tt \$mem} cell.
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\item \B{SIZE} \\
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The number of words in the memory.
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\item \B{ABITS} \\
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The number of address bits.
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\item \B{WIDTH} \\
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The number of data bits per word.
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\item \B{INIT} \\
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The initial memory contents.
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\item \B{RD\_PORTS} \\
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The number of read ports on this memory cell.
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\item \B{RD\_CLK\_ENABLE} \\
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This parameter is \B{RD\_PORTS} bits wide, containing a clock enable bit for each read port.
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\item \B{RD\_CLK\_POLARITY} \\
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This parameter is \B{RD\_PORTS} bits wide, containing a clock polarity bit for each read port.
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\item \B{RD\_TRANSPARENT} \\
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This parameter is \B{RD\_PORTS} bits wide, containing a transparent bit for each read port.
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\item \B{WR\_PORTS} \\
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The number of write ports on this memory cell.
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\item \B{WR\_CLK\_ENABLE} \\
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This parameter is \B{WR\_PORTS} bits wide, containing a clock enable bit for each write port.
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\item \B{WR\_CLK\_POLARITY} \\
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This parameter is \B{WR\_PORTS} bits wide, containing a clock polarity bit for each write port.
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\end{itemize}
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The {\tt \$mem} cell has the following ports:
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\begin{itemize}
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\item \B{RD\_CLK} \\
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This input is \B{RD\_PORTS} bits wide, containing all clock signals for the read ports.
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|
|
\item \B{RD\_EN} \\
|
|
This input is \B{RD\_PORTS} bits wide, containing all enable signals for the read ports.
|
|
|
|
\item \B{RD\_ADDR} \\
|
|
This input is \B{RD\_PORTS}*\B{ABITS} bits wide, containing all address signals for the read ports.
|
|
|
|
\item \B{RD\_DATA} \\
|
|
This input is \B{RD\_PORTS}*\B{WIDTH} bits wide, containing all data signals for the read ports.
|
|
|
|
\item \B{WR\_CLK} \\
|
|
This input is \B{WR\_PORTS} bits wide, containing all clock signals for the write ports.
|
|
|
|
\item \B{WR\_EN} \\
|
|
This input is \B{WR\_PORTS}*\B{WIDTH} bits wide, containing all enable signals for the write ports.
|
|
|
|
\item \B{WR\_ADDR} \\
|
|
This input is \B{WR\_PORTS}*\B{ABITS} bits wide, containing all address signals for the write ports.
|
|
|
|
\item \B{WR\_DATA} \\
|
|
This input is \B{WR\_PORTS}*\B{WIDTH} bits wide, containing all data signals for the write ports.
|
|
\end{itemize}
|
|
|
|
The {\tt memory\_collect} pass can be used to convert discrete {\tt \$memrd}, {\tt \$memwr}, and {\tt \$meminit} cells
|
|
belonging to the same memory to a single {\tt \$mem} cell, whereas the {\tt memory\_unpack} pass performs the inverse operation.
|
|
The {\tt memory\_dff} pass can combine asynchronous memory ports that are fed by or feeding registers into synchronous memory ports.
|
|
The {\tt memory\_bram} pass can be used to recognize {\tt \$mem} cells that can be implemented with a block RAM resource on an FPGA.
|
|
The {\tt memory\_map} pass can be used to implement {\tt \$mem} cells as basic logic: word-wide DFFs and address decoders.
|
|
|
|
\subsection{Finite State Machines}
|
|
|
|
\begin{fixme}
|
|
Add a brief description of the {\tt \$fsm} cell type.
|
|
\end{fixme}
|
|
|
|
\section{Gates}
|
|
\label{sec:celllib_gates}
|
|
|
|
For gate level logic networks, fixed function single bit cells are used that do
|
|
not provide any parameters.
|
|
|
|
Simulation models for these cells can be found in the file {\tt techlibs/common/simcells.v} in the Yosys
|
|
source tree.
|
|
|
|
\begin{table}[t]
|
|
\hfil
|
|
\begin{tabular}[t]{ll}
|
|
Verilog & Cell Type \\
|
|
\hline
|
|
\lstinline[language=Verilog]; Y = ~A; & {\tt \$\_NOT\_} \\
|
|
\lstinline[language=Verilog]; Y = A & B; & {\tt \$\_AND\_} \\
|
|
\lstinline[language=Verilog]; Y = ~(A & B); & {\tt \$\_NAND\_} \\
|
|
\lstinline[language=Verilog]; Y = A & ~B; & {\tt \$\_ANDNOT\_} \\
|
|
\lstinline[language=Verilog]; Y = A | B; & {\tt \$\_OR\_} \\
|
|
\lstinline[language=Verilog]; Y = ~(A | B); & {\tt \$\_NOR\_} \\
|
|
\lstinline[language=Verilog]; Y = A | ~B; & {\tt \$\_ORNOT\_} \\
|
|
\lstinline[language=Verilog]; Y = A ^ B; & {\tt \$\_XOR\_} \\
|
|
\lstinline[language=Verilog]; Y = ~(A ^ B); & {\tt \$\_XNOR\_} \\
|
|
\lstinline[language=Verilog]; Y = S ? B : A; & {\tt \$\_MUX\_} \\
|
|
\lstinline[language=Verilog]; Y = EN ? A : 'bz; & {\tt \$\_TBUF\_} \\
|
|
\hline
|
|
\lstinline[language=Verilog]; always @(negedge C) Q <= D; & {\tt \$\_DFF\_N\_} \\
|
|
\lstinline[language=Verilog]; always @(posedge C) Q <= D; & {\tt \$\_DFF\_P\_} \\
|
|
\end{tabular}
|
|
\hfil
|
|
\begin{tabular}[t]{llll}
|
|
$ClkEdge$ & $RstLvl$ & $RstVal$ & Cell Type \\
|
|
\hline
|
|
\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFF\_NN0\_} \\
|
|
\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFF\_NN1\_} \\
|
|
\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFF\_NP0\_} \\
|
|
\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFF\_NP1\_} \\
|
|
\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFF\_PN0\_} \\
|
|
\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFF\_PN1\_} \\
|
|
\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFF\_PP0\_} \\
|
|
\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFF\_PP1\_} \\
|
|
\end{tabular}
|
|
% FIXME: the layout of this is broken and I have no idea how to fix it
|
|
\hfil
|
|
\begin{tabular}[t]{lll}
|
|
$ClkEdge$ & $EnLvl$ & Cell Type \\
|
|
\hline
|
|
\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_NN\_} \\
|
|
\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_NP\_} \\
|
|
\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_PN\_} \\
|
|
\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_PP\_} \\
|
|
\end{tabular}
|
|
% FIXME: the layout of this is broken too
|
|
\hfil
|
|
\begin{tabular}[t]{llll}
|
|
$ClkEdge$ & $SetLvl$ & $RstLvl$ & Cell Type \\
|
|
\hline
|
|
\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSR\_NNN\_} \\
|
|
\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSR\_NNP\_} \\
|
|
\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSR\_NPN\_} \\
|
|
\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSR\_NPP\_} \\
|
|
\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSR\_PNN\_} \\
|
|
\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSR\_PNP\_} \\
|
|
\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSR\_PPN\_} \\
|
|
\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSR\_PPP\_} \\
|
|
\end{tabular}
|
|
\caption{Cell types for gate level logic networks}
|
|
\label{tab:CellLib_gates}
|
|
\end{table}
|
|
|
|
Table~\ref{tab:CellLib_gates} lists all cell types used for gate level logic. The cell types
|
|
{\tt \$\_NOT\_}, {\tt \$\_AND\_}, {\tt \$\_NAND\_}, {\tt \$\_ANDNOT\_}, {\tt \$\_OR\_}, {\tt \$\_NOR\_},
|
|
{\tt \$\_ORNOT\_}, {\tt \$\_XOR\_}, {\tt \$\_XNOR\_} and {\tt \$\_MUX\_} are used to model combinatorial logic.
|
|
The cell type {\tt \$\_TBUF\_} is used to model tristate logic.
|
|
|
|
The cell types {\tt \$\_DFF\_N\_} and {\tt \$\_DFF\_P\_} represent d-type flip-flops.
|
|
|
|
The cell types {\tt \$\_DFFE\_NN\_}, {\tt \$\_DFFE\_NP\_}, {\tt \$\_DFFE\_PN\_} and {\tt \$\_DFFE\_PP\_}
|
|
implement d-type flip-flops with enable. The values in the table for these cell types relate to the
|
|
following Verilog code template.
|
|
|
|
\begin{lstlisting}[mathescape,language=Verilog]
|
|
always @($ClkEdge$ C)
|
|
if (EN == $EnLvl$)
|
|
Q <= D;
|
|
\end{lstlisting}
|
|
|
|
The cell types {\tt \$\_DFF\_NN0\_}, {\tt \$\_DFF\_NN1\_}, {\tt \$\_DFF\_NP0\_}, {\tt \$\_DFF\_NP1\_},
|
|
{\tt \$\_DFF\_PN0\_}, {\tt \$\_DFF\_PN1\_}, {\tt \$\_DFF\_PP0\_} and {\tt \$\_DFF\_PP1\_} implement
|
|
d-type flip-flops with asynchronous reset. The values in the table for these cell types relate to the
|
|
following Verilog code template, where \lstinline[mathescape,language=Verilog];$RstEdge$; is \lstinline[language=Verilog];posedge;
|
|
if \lstinline[mathescape,language=Verilog];$RstLvl$; if \lstinline[language=Verilog];1;, and \lstinline[language=Verilog];negedge;
|
|
otherwise.
|
|
|
|
\begin{lstlisting}[mathescape,language=Verilog]
|
|
always @($ClkEdge$ C, $RstEdge$ R)
|
|
if (R == $RstLvl$)
|
|
Q <= $RstVal$;
|
|
else
|
|
Q <= D;
|
|
\end{lstlisting}
|
|
|
|
The cell types {\tt \$\_DFFSR\_NNN\_}, {\tt \$\_DFFSR\_NNP\_}, {\tt \$\_DFFSR\_NPN\_}, {\tt \$\_DFFSR\_NPP\_},
|
|
{\tt \$\_DFFSR\_PNN\_}, {\tt \$\_DFFSR\_PNP\_}, {\tt \$\_DFFSR\_PPN\_} and {\tt \$\_DFFSR\_PPP\_} implement
|
|
d-type flip-flops with asynchronous set and reset. The values in the table for these cell types relate to the
|
|
following Verilog code template, where \lstinline[mathescape,language=Verilog];$RstEdge$; is \lstinline[language=Verilog];posedge;
|
|
if \lstinline[mathescape,language=Verilog];$RstLvl$; if \lstinline[language=Verilog];1;, \lstinline[language=Verilog];negedge;
|
|
otherwise, and \lstinline[mathescape,language=Verilog];$SetEdge$; is \lstinline[language=Verilog];posedge;
|
|
if \lstinline[mathescape,language=Verilog];$SetLvl$; if \lstinline[language=Verilog];1;, \lstinline[language=Verilog];negedge;
|
|
otherwise.
|
|
|
|
\begin{lstlisting}[mathescape,language=Verilog]
|
|
always @($ClkEdge$ C, $RstEdge$ R, $SetEdge$ S)
|
|
if (R == $RstLvl$)
|
|
Q <= 0;
|
|
else if (S == $SetLvl$)
|
|
Q <= 1;
|
|
else
|
|
Q <= D;
|
|
\end{lstlisting}
|
|
|
|
In most cases gate level logic networks are created from RTL networks using the {\tt techmap} pass. The flip-flop cells
|
|
from the gate level logic network can be mapped to physical flip-flop cells from a Liberty file using the {\tt dfflibmap}
|
|
pass. The combinatorial logic cells can be mapped to physical cells from a Liberty file via ABC \citeweblink{ABC}
|
|
using the {\tt abc} pass.
|
|
|
|
\begin{fixme}
|
|
Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$live}, {\tt \$fair}, {\tt \$cover}, {\tt \$equiv},
|
|
{\tt \$initstate}, {\tt \$anyconst}, {\tt \$anyseq}, {\tt \$allconst}, {\tt \$allseq} cells.
|
|
\end{fixme}
|
|
|
|
\begin{fixme}
|
|
Add information about {\tt \$specify2}, {\tt \$specify3}, and {\tt \$specrule} cells.
|
|
\end{fixme}
|
|
|
|
\begin{fixme}
|
|
Add information about {\tt \$slice} and {\tt \$concat} cells.
|
|
\end{fixme}
|
|
|
|
\begin{fixme}
|
|
Add information about {\tt \$lut} and {\tt \$sop} cells.
|
|
\end{fixme}
|
|
|
|
\begin{fixme}
|
|
Add information about {\tt \$alu}, {\tt \$macc}, {\tt \$fa}, and {\tt \$lcu} cells.
|
|
\end{fixme}
|
|
|
|
\begin{fixme}
|
|
Add information about {\tt \$ff} and {\tt \$\_FF\_} cells.
|
|
\end{fixme}
|
|
|
|
\begin{fixme}
|
|
Add information about {\tt \$\_DLATCH\_?\_}, and {\tt \$\_DLATCHSR\_???\_} cells.
|
|
\end{fixme}
|
|
|
|
\begin{fixme}
|
|
Add information about {\tt \$\_AOI3\_}, {\tt \$\_OAI3\_}, {\tt \$\_AOI4\_}, {\tt \$\_OAI4\_}, and {\tt \$\_NMUX\_} cells.
|
|
\end{fixme}
|
|
|