mirror of https://github.com/YosysHQ/yosys.git
717 lines
22 KiB
C++
717 lines
22 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// [[CITE]] ABC
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// Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
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// http://www.eecs.berkeley.edu/~alanmi/abc/
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// [[CITE]] Kahn's Topological sorting algorithm
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// Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558–562, doi:10.1145/368996.369025
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// http://en.wikipedia.org/wiki/Topological_sorting
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "vlparse.h"
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#include <unistd.h>
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#include <stdlib.h>
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#include <assert.h>
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#include <stdio.h>
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#include <string.h>
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#include <dirent.h>
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#include <sstream>
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struct gate_t
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{
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int id;
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char type;
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int in1, in2, in3;
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bool is_port;
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RTLIL::SigSpec sig;
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};
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static int map_autoidx;
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static SigMap assign_map;
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static RTLIL::Module *module;
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static std::vector<gate_t> signal_list;
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static std::map<RTLIL::SigSpec, int> signal_map;
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static int map_signal(RTLIL::SigSpec sig, char gate_type = -1, int in1 = -1, int in2 = -1, int in3 = -1)
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{
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assert(sig.width == 1);
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assert(sig.chunks.size() == 1);
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assign_map.apply(sig);
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if (signal_map.count(sig) == 0) {
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gate_t gate;
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gate.id = signal_list.size();
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gate.type = -1;
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gate.in1 = -1;
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gate.in2 = -1;
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gate.in3 = -1;
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gate.is_port = false;
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gate.sig = sig;
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signal_list.push_back(gate);
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signal_map[sig] = gate.id;
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}
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gate_t &gate = signal_list[signal_map[sig]];
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if (gate_type >= 0)
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gate.type = gate_type;
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if (in1 >= 0)
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gate.in1 = in1;
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if (in2 >= 0)
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gate.in2 = in2;
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if (in3 >= 0)
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gate.in3 = in3;
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return gate.id;
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}
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static void mark_port(RTLIL::SigSpec sig)
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{
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assign_map.apply(sig);
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sig.expand();
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for (auto &c : sig.chunks) {
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if (c.wire != NULL && signal_map.count(c) > 0)
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signal_list[signal_map[c]].is_port = true;
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}
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}
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static void extract_cell(RTLIL::Cell *cell)
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{
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if (cell->type == "$_INV_")
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{
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RTLIL::SigSpec sig_a = cell->connections["\\A"];
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RTLIL::SigSpec sig_y = cell->connections["\\Y"];
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assign_map.apply(sig_a);
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assign_map.apply(sig_y);
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map_signal(sig_y, 'n', map_signal(sig_a));
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module->cells.erase(cell->name);
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delete cell;
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return;
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}
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if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_")
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{
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RTLIL::SigSpec sig_a = cell->connections["\\A"];
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RTLIL::SigSpec sig_b = cell->connections["\\B"];
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RTLIL::SigSpec sig_y = cell->connections["\\Y"];
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assign_map.apply(sig_a);
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assign_map.apply(sig_b);
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assign_map.apply(sig_y);
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int mapped_a = map_signal(sig_a);
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int mapped_b = map_signal(sig_b);
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if (cell->type == "$_AND_")
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map_signal(sig_y, 'a', mapped_a, mapped_b);
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else if (cell->type == "$_OR_")
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map_signal(sig_y, 'o', mapped_a, mapped_b);
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else if (cell->type == "$_XOR_")
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map_signal(sig_y, 'x', mapped_a, mapped_b);
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else
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abort();
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module->cells.erase(cell->name);
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delete cell;
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return;
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}
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if (cell->type == "$_MUX_")
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{
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RTLIL::SigSpec sig_a = cell->connections["\\A"];
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RTLIL::SigSpec sig_b = cell->connections["\\B"];
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RTLIL::SigSpec sig_s = cell->connections["\\S"];
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RTLIL::SigSpec sig_y = cell->connections["\\Y"];
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assign_map.apply(sig_a);
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assign_map.apply(sig_b);
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assign_map.apply(sig_s);
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assign_map.apply(sig_y);
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int mapped_a = map_signal(sig_a);
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int mapped_b = map_signal(sig_b);
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int mapped_s = map_signal(sig_s);
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map_signal(sig_y, 'm', mapped_a, mapped_b, mapped_s);
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module->cells.erase(cell->name);
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delete cell;
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return;
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}
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}
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static std::string remap_name(std::string abc_name)
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{
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std::stringstream sstr;
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sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
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return sstr.str();
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}
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static void dump_loop_graph(FILE *f, int &nr, std::map<int, std::set<int>> &edges, std::set<int> &workpool, std::vector<int> &in_counts)
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{
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if (f == NULL)
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return;
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log("Dumping loop state graph to slide %d.\n", ++nr);
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fprintf(f, "digraph slide%d {\n", nr);
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fprintf(f, " rankdir=\"LR\";\n");
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std::set<int> nodes;
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for (auto &e : edges) {
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nodes.insert(e.first);
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for (auto n : e.second)
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nodes.insert(n);
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}
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for (auto n : nodes)
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fprintf(f, " n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].sig),
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n, in_counts[n], workpool.count(n) ? ", shape=box" : "");
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for (auto &e : edges)
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for (auto n : e.second)
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fprintf(f, " n%d -> n%d;\n", e.first, n);
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fprintf(f, "}\n");
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}
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static void handle_loops()
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{
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// http://en.wikipedia.org/wiki/Topological_sorting
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// (Kahn, Arthur B. (1962), "Topological sorting of large networks")
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std::map<int, std::set<int>> edges;
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std::vector<int> in_edges_count(signal_list.size());
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std::set<int> workpool;
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FILE *dot_f = NULL;
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int dot_nr = 0;
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// uncomment for troubleshooting the loop detection code
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// dot_f = fopen("test.dot", "w");
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for (auto &g : signal_list) {
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if (g.type == -1) {
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workpool.insert(g.id);
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}
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if (g.in1 >= 0) {
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edges[g.in1].insert(g.id);
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in_edges_count[g.id]++;
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}
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if (g.in2 >= 0 && g.in2 != g.in1) {
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edges[g.in2].insert(g.id);
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in_edges_count[g.id]++;
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}
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if (g.in3 >= 0 && g.in3 != g.in2 && g.in3 != g.in1) {
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edges[g.in3].insert(g.id);
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in_edges_count[g.id]++;
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}
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}
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dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count);
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while (workpool.size() > 0)
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{
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int id = *workpool.begin();
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workpool.erase(id);
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// log("Removing non-loop node %d from graph: %s\n", id, log_signal(signal_list[id].sig));
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for (int id2 : edges[id]) {
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assert(in_edges_count[id2] > 0);
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if (--in_edges_count[id2] == 0)
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workpool.insert(id2);
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}
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edges.erase(id);
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dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count);
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while (workpool.size() == 0)
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{
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if (edges.size() == 0)
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break;
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int id1 = edges.begin()->first;
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for (auto &edge_it : edges) {
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int id2 = edge_it.first;
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RTLIL::Wire *w1 = signal_list[id1].sig.chunks[0].wire;
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RTLIL::Wire *w2 = signal_list[id2].sig.chunks[0].wire;
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if (w1 != NULL)
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continue;
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else if (w2 == NULL)
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id1 = id2;
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else if (w1->name[0] == '$' && w2->name[0] == '\\')
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id1 = id2;
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else if (w1->name[0] == '\\' && w2->name[0] == '$')
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continue;
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else if (edges[id1].size() < edges[id2].size())
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id1 = id2;
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else if (edges[id1].size() > edges[id2].size())
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continue;
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else if (w1->name > w2->name)
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id1 = id2;
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}
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if (edges[id1].size() == 0) {
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edges.erase(id1);
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continue;
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}
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RTLIL::Wire *wire = new RTLIL::Wire;
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std::stringstream sstr;
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sstr << "$abcloop$" << (RTLIL::autoidx++);
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wire->name = sstr.str();
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module->wires[wire->name] = wire;
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bool first_line = true;
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for (int id2 : edges[id1]) {
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if (first_line)
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log("Breaking loop using new signal %s: %s -> %s\n", log_signal(RTLIL::SigSpec(wire)),
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log_signal(signal_list[id1].sig), log_signal(signal_list[id2].sig));
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else
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log(" %*s %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire)))), "",
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log_signal(signal_list[id1].sig), log_signal(signal_list[id2].sig));
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first_line = false;
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}
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int id3 = map_signal(RTLIL::SigSpec(wire));
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signal_list[id1].is_port = true;
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signal_list[id3].is_port = true;
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assert(id3 == int(in_edges_count.size()));
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in_edges_count.push_back(0);
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workpool.insert(id3);
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for (int id2 : edges[id1]) {
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if (signal_list[id2].in1 == id1)
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signal_list[id2].in1 = id3;
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if (signal_list[id2].in2 == id1)
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signal_list[id2].in2 = id3;
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if (signal_list[id2].in3 == id1)
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signal_list[id2].in3 = id3;
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}
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edges[id1].swap(edges[id3]);
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module->connections.push_back(RTLIL::SigSig(signal_list[id3].sig, signal_list[id1].sig));
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dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count);
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}
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}
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if (dot_f != NULL)
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fclose(dot_f);
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}
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static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, bool cleanup)
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{
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module = current_module;
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map_autoidx = RTLIL::autoidx++;
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signal_map.clear();
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signal_list.clear();
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assign_map.set(module);
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char tempdir_name[] = "/tmp/yosys-abc-XXXXXX";
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if (!cleanup)
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tempdir_name[0] = tempdir_name[4] = '_';
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char *p = mkdtemp(tempdir_name);
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log_header("Extracting gate logic of module `%s' to `%s/input.v'..\n", module->name.c_str(), tempdir_name);
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if (p == NULL)
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log_error("For some reason mkdtemp() failed!\n");
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std::vector<RTLIL::Cell*> cells;
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cells.reserve(module->cells.size());
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for (auto &it : module->cells)
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if (design->selected(current_module, it.second))
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cells.push_back(it.second);
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for (auto c : cells)
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extract_cell(c);
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for (auto &wire_it : module->wires) {
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if (wire_it.second->port_id > 0)
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mark_port(RTLIL::SigSpec(wire_it.second));
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}
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for (auto &cell_it : module->cells)
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for (auto &port_it : cell_it.second->connections)
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mark_port(port_it.second);
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handle_loops();
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if (asprintf(&p, "%s/input.v", tempdir_name) < 0) abort();
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FILE *f = fopen(p, "wt");
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if (f == NULL)
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log_error("Opening %s for writing failed: %s\n", p, strerror(errno));
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free(p);
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fprintf(f, "module logic (");
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bool first = true;
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for (auto &si : signal_list) {
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if (!si.is_port)
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continue;
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if (!first)
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fprintf(f, ", ");
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fprintf(f, "n%d", si.id);
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first = false;
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}
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fprintf(f, "); // %s\n", module->name.c_str());
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int count_input = 0, count_output = 0;
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for (auto &si : signal_list) {
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if (si.is_port) {
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if (si.type >= 0)
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count_output++;
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else
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count_input++;
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}
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fprintf(f, "%s n%d; // %s\n", si.is_port ? si.type >= 0 ?
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"output" : "input" : "wire", si.id, log_signal(si.sig));
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}
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for (auto &si : signal_list) {
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assert(si.sig.width == 1 && si.sig.chunks.size() == 1);
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if (si.sig.chunks[0].wire == NULL)
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fprintf(f, "assign n%d = %c;\n", si.id, si.sig.chunks[0].data.bits[0] == RTLIL::State::S1 ? '1' : '0');
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}
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int count_gates = 0;
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for (auto &si : signal_list) {
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if (si.type == 'n')
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fprintf(f, "not (n%d, n%d);\n", si.id, si.in1);
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else if (si.type == 'a')
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fprintf(f, "and (n%d, n%d, n%d);\n", si.id, si.in1, si.in2);
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else if (si.type == 'o')
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fprintf(f, "or (n%d, n%d, n%d);\n", si.id, si.in1, si.in2);
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else if (si.type == 'x')
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fprintf(f, "xor (n%d, n%d, n%d);\n", si.id, si.in1, si.in2);
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else if (si.type == 'm')
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fprintf(f, "assign n%d = n%d ? n%d : n%d;\n", si.id, si.in3, si.in2, si.in1);
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else if (si.type >= 0)
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abort();
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if (si.type >= 0)
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count_gates++;
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}
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fprintf(f, "endmodule\n");
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fclose(f);
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log("Extracted %d gates and %zd wires to a logic network with %d inputs and %d outputs.\n",
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count_gates, signal_list.size(), count_input, count_output);
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log_push();
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if (count_output > 0)
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{
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log_header("Executing ABC.\n");
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if (asprintf(&p, "%s/stdcells.genlib", tempdir_name) < 0) abort();
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f = fopen(p, "wt");
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if (f == NULL)
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log_error("Opening %s for writing failed: %s\n", p, strerror(errno));
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fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
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fprintf(f, "GATE ONE 1 Y=CONST1;\n");
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fprintf(f, "GATE BUF 1 Y=A; PIN * NONINV 1 999 1 0 1 0\n");
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fprintf(f, "GATE INV 1 Y=!A; PIN * INV 1 999 1 0 1 0\n");
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fprintf(f, "GATE AND 1 Y=A*B; PIN * NONINV 1 999 1 0 1 0\n");
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fprintf(f, "GATE OR 1 Y=A+B; PIN * NONINV 1 999 1 0 1 0\n");
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fprintf(f, "GATE XOR 1 Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n");
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fprintf(f, "GATE MUX 1 Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n");
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fclose(f);
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free(p);
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char buffer[1024];
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if (!liberty_file.empty())
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snprintf(buffer, 1024, "%s -c 'read_verilog %s/input.v; read_liberty %s; "
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"map; write_verilog %s/output.v' 2>&1", exe_file.c_str(), tempdir_name, liberty_file.c_str(), tempdir_name);
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else
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if (!script_file.empty())
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snprintf(buffer, 1024, "%s -c 'read_verilog %s/input.v; source %s; "
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"map; write_verilog %s/output.v' 2>&1", exe_file.c_str(), tempdir_name, script_file.c_str(), tempdir_name);
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else
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snprintf(buffer, 1024, "%s -c 'read_verilog %s/input.v; read_library %s/stdcells.genlib; "
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"map; write_verilog %s/output.v' 2>&1", exe_file.c_str(), tempdir_name, tempdir_name, tempdir_name);
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errno = ENOMEM; // popen does not set errno if memory allocation fails, therefore set it by hand
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f = popen(buffer, "r");
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if (f == NULL)
|
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log_error("Opening pipe to `%s' for reading failed: %s\n", buffer, strerror(errno));
|
||
while (fgets(buffer, 1024, f) != NULL)
|
||
log("ABC: %s", buffer);
|
||
errno = 0;
|
||
int ret = pclose(f);
|
||
if (ret < 0)
|
||
log_error("Closing pipe to `%s' failed: %s\n", buffer, strerror(errno));
|
||
if (WEXITSTATUS(ret) != 0) {
|
||
switch (WEXITSTATUS(ret)) {
|
||
case 127: log_error("ABC: execution of command \"%s\" failed: Command not found\n", exe_file.c_str()); break;
|
||
case 126: log_error("ABC: execution of command \"%s\" failed: Command not executable\n", exe_file.c_str()); break;
|
||
default: log_error("ABC: execution of command \"%s\" failed: the shell returned %d\n", exe_file.c_str(), WEXITSTATUS(ret)); break;
|
||
}
|
||
}
|
||
|
||
if (asprintf(&p, "%s/output.v", tempdir_name) < 0) abort();
|
||
f = fopen(p, "rt");
|
||
if (f == NULL)
|
||
log_error("Can't open ABC output file `%s'.\n", p);
|
||
#if 0
|
||
RTLIL::Design *mapped_design = new RTLIL::Design;
|
||
frontend_register["verilog"]->execute(f, p, std::vector<std::string>(), mapped_design);
|
||
#else
|
||
RTLIL::Design *mapped_design = abc_parse_verilog(f);
|
||
#endif
|
||
fclose(f);
|
||
free(p);
|
||
|
||
log_header("Re-integrating ABC results.\n");
|
||
RTLIL::Module *mapped_mod = mapped_design->modules["\\logic"];
|
||
if (mapped_mod == NULL)
|
||
log_error("ABC output file does not contain a module `logic'.\n");
|
||
for (auto &it : mapped_mod->wires) {
|
||
RTLIL::Wire *w = it.second;
|
||
RTLIL::Wire *wire = new RTLIL::Wire;
|
||
wire->name = remap_name(w->name);
|
||
module->wires[wire->name] = wire;
|
||
design->select(module, wire);
|
||
}
|
||
|
||
std::map<std::string, int> cell_stats;
|
||
if (liberty_file.empty() && script_file.empty())
|
||
{
|
||
for (auto &it : mapped_mod->cells) {
|
||
RTLIL::Cell *c = it.second;
|
||
cell_stats[c->type.substr(1)]++;
|
||
if (c->type == "\\ZERO" || c->type == "\\ONE") {
|
||
RTLIL::SigSig conn;
|
||
conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]);
|
||
conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1);
|
||
module->connections.push_back(conn);
|
||
continue;
|
||
}
|
||
if (c->type == "\\BUF") {
|
||
RTLIL::SigSig conn;
|
||
conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]);
|
||
conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks[0].wire->name)]);
|
||
module->connections.push_back(conn);
|
||
continue;
|
||
}
|
||
if (c->type == "\\INV") {
|
||
RTLIL::Cell *cell = new RTLIL::Cell;
|
||
cell->type = "$_INV_";
|
||
cell->name = remap_name(c->name);
|
||
cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks[0].wire->name)]);
|
||
cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]);
|
||
module->cells[cell->name] = cell;
|
||
design->select(module, cell);
|
||
continue;
|
||
}
|
||
if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR") {
|
||
RTLIL::Cell *cell = new RTLIL::Cell;
|
||
cell->type = "$_" + c->type.substr(1) + "_";
|
||
cell->name = remap_name(c->name);
|
||
cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks[0].wire->name)]);
|
||
cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks[0].wire->name)]);
|
||
cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]);
|
||
module->cells[cell->name] = cell;
|
||
design->select(module, cell);
|
||
continue;
|
||
}
|
||
if (c->type == "\\MUX") {
|
||
RTLIL::Cell *cell = new RTLIL::Cell;
|
||
cell->type = "$_MUX_";
|
||
cell->name = remap_name(c->name);
|
||
cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks[0].wire->name)]);
|
||
cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks[0].wire->name)]);
|
||
cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].chunks[0].wire->name)]);
|
||
cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]);
|
||
module->cells[cell->name] = cell;
|
||
design->select(module, cell);
|
||
continue;
|
||
}
|
||
assert(0);
|
||
}
|
||
}
|
||
else
|
||
{
|
||
for (auto &it : mapped_mod->cells) {
|
||
RTLIL::Cell *c = it.second;
|
||
cell_stats[c->type.substr(1)]++;
|
||
if (c->type == "$_const0_" || c->type == "$_const1_") {
|
||
RTLIL::SigSig conn;
|
||
conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]);
|
||
conn.second = RTLIL::SigSpec(c->type == "$_const0_" ? 0 : 1, 1);
|
||
module->connections.push_back(conn);
|
||
continue;
|
||
}
|
||
RTLIL::Cell *cell = new RTLIL::Cell;
|
||
cell->type = c->type;
|
||
cell->name = remap_name(c->name);
|
||
for (auto &conn : c->connections)
|
||
cell->connections[conn.first] = RTLIL::SigSpec(module->wires[remap_name(conn.second.chunks[0].wire->name)]);
|
||
module->cells[cell->name] = cell;
|
||
design->select(module, cell);
|
||
}
|
||
}
|
||
|
||
for (auto &it : cell_stats)
|
||
log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
|
||
int in_wires = 0, out_wires = 0;
|
||
for (auto &si : signal_list)
|
||
if (si.is_port) {
|
||
char buffer[100];
|
||
snprintf(buffer, 100, "\\n%d", si.id);
|
||
RTLIL::SigSig conn;
|
||
if (si.type >= 0) {
|
||
conn.first = si.sig;
|
||
conn.second = RTLIL::SigSpec(module->wires[remap_name(buffer)]);
|
||
out_wires++;
|
||
} else {
|
||
conn.first = RTLIL::SigSpec(module->wires[remap_name(buffer)]);
|
||
conn.second = si.sig;
|
||
in_wires++;
|
||
}
|
||
module->connections.push_back(conn);
|
||
}
|
||
log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
|
||
log("ABC RESULTS: input signals: %8d\n", in_wires);
|
||
log("ABC RESULTS: output signals: %8d\n", out_wires);
|
||
|
||
delete mapped_design;
|
||
}
|
||
else
|
||
{
|
||
log("Don't call ABC as there is nothing to map.\n");
|
||
}
|
||
|
||
if (cleanup)
|
||
{
|
||
log_header("Removing temp directory `%s':\n", tempdir_name);
|
||
|
||
struct dirent **namelist;
|
||
int n = scandir(tempdir_name, &namelist, 0, alphasort);
|
||
assert(n >= 0);
|
||
for (int i = 0; i < n; i++) {
|
||
if (strcmp(namelist[i]->d_name, ".") && strcmp(namelist[i]->d_name, "..")) {
|
||
if (asprintf(&p, "%s/%s", tempdir_name, namelist[i]->d_name) < 0) abort();
|
||
log("Removing `%s'.\n", p);
|
||
remove(p);
|
||
free(p);
|
||
}
|
||
free(namelist[i]);
|
||
}
|
||
free(namelist);
|
||
log("Removing `%s'.\n", tempdir_name);
|
||
rmdir(tempdir_name);
|
||
}
|
||
|
||
log_pop();
|
||
}
|
||
|
||
struct AbcPass : public Pass {
|
||
AbcPass() : Pass("abc", "use ABC for technology mapping") { }
|
||
virtual void help()
|
||
{
|
||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||
log("\n");
|
||
log(" abc [options] [selection]\n");
|
||
log("\n");
|
||
log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
|
||
log("library to a target architecture.\n");
|
||
log("\n");
|
||
log(" -exe <command>\n");
|
||
log(" use the specified command name instead of \"yosys-abc\" to execute ABC.\n");
|
||
log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
|
||
log("\n");
|
||
log(" -script <file>\n");
|
||
log(" use the specified ABC script file instead of the default script.\n");
|
||
log("\n");
|
||
log(" -liberty <file>\n");
|
||
log(" generate netlists for the specified cell library (using the liberty\n");
|
||
log(" file format). Without this option, ABC is used to optimize the netlist\n");
|
||
log(" but keeps using yosys's internal gate library. This option is ignored if\n");
|
||
log(" the -script option is also used.\n");
|
||
log("\n");
|
||
log(" -nocleanup\n");
|
||
log(" when this option is used, the temporary files created by this pass\n");
|
||
log(" are not removed. this is useful for debugging.\n");
|
||
log("\n");
|
||
log("This pass does not operate on modules with unprocessed processes in it.\n");
|
||
log("(I.e. the 'proc' pass should be used first to convert processes to netlists.)\n");
|
||
log("\n");
|
||
log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
|
||
log("\n");
|
||
}
|
||
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
|
||
{
|
||
log_header("Executing ABC pass (technology mapping using ABC).\n");
|
||
log_push();
|
||
|
||
std::string exe_file = "yosys-abc";
|
||
std::string script_file, liberty_file;
|
||
bool cleanup = true;
|
||
|
||
size_t argidx;
|
||
char *pwd = get_current_dir_name();
|
||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||
std::string arg = args[argidx];
|
||
if (arg == "-exe" && argidx+1 < args.size()) {
|
||
exe_file = args[++argidx];
|
||
continue;
|
||
}
|
||
if (arg == "-script" && argidx+1 < args.size() && liberty_file.empty()) {
|
||
script_file = args[++argidx];
|
||
if (!script_file.empty() && script_file[0] != '/')
|
||
script_file = std::string(pwd) + "/" + script_file;
|
||
continue;
|
||
}
|
||
if (arg == "-liberty" && argidx+1 < args.size() && script_file.empty()) {
|
||
liberty_file = args[++argidx];
|
||
if (!liberty_file.empty() && liberty_file[0] != '/')
|
||
liberty_file = std::string(pwd) + "/" + liberty_file;
|
||
continue;
|
||
}
|
||
if (arg == "-nocleanup") {
|
||
cleanup = false;
|
||
continue;
|
||
}
|
||
break;
|
||
}
|
||
free(pwd);
|
||
extra_args(args, argidx, design);
|
||
|
||
for (auto &mod_it : design->modules)
|
||
if (design->selected(mod_it.second)) {
|
||
if (mod_it.second->processes.size() > 0)
|
||
log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
|
||
else
|
||
abc_module(design, mod_it.second, script_file, exe_file, liberty_file, cleanup);
|
||
}
|
||
|
||
assign_map.clear();
|
||
signal_list.clear();
|
||
signal_map.clear();
|
||
|
||
log_pop();
|
||
}
|
||
} AbcPass;
|
||
|