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68 lines
2.5 KiB
ReStructuredText
68 lines
2.5 KiB
ReStructuredText
Converting process blocks
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~~~~~~~~~~~~~~~~~~~~~~~~~
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The Verilog frontend converts ``always``-blocks to RTL netlists for the
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expressions and "processess" for the control- and memory elements. The
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:cmd:ref:`proc` command then transforms these "processess" to netlists of RTL
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multiplexer and register cells. It also is a macro command that calls the other
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``proc_*`` commands in a sensible order:
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#. :cmd:ref:`proc_clean` removes empty branches and processes.
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#. :cmd:ref:`proc_rmdead` removes unreachable branches.
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#. :cmd:ref:`proc_prune`
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#. :cmd:ref:`proc_init` special handling of "initial" blocks.
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#. :cmd:ref:`proc_arst` identifies modeling of async resets.
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#. :cmd:ref:`proc_rom`
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#. :cmd:ref:`proc_mux` converts decision trees to multiplexer networks.
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#. :cmd:ref:`proc_dlatch`
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#. :cmd:ref:`proc_dff` extracts registers from processes.
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#. :cmd:ref:`proc_memwr`
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#. :cmd:ref:`proc_clean` this should remove all the processes, provided all went
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fine.
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After all the ``proc_*`` commands, :yoscrypt:`opt_expr` is called. This can be
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disabled by calling :yoscrypt:`proc -noopt`. For more information about
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:cmd:ref:`proc`, such as disabling certain sub commands, see :doc:`/cmd/proc`.
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Many commands can not operate on modules with "processess" in them. Usually a
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call to :cmd:ref:`proc` is the first command in the actual synthesis procedure
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after design elaboration.
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Example
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^^^^^^^
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.. todo:: describe ``proc`` images
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.. literalinclude:: /code_examples/synth_flow/proc_01.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/proc_01.v``
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.. literalinclude:: /code_examples/synth_flow/proc_01.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/proc_01.ys``
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.. figure:: /_images/code_examples/synth_flow/proc_01.*
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:class: width-helper
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.. figure:: /_images/code_examples/synth_flow/proc_02.*
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:class: width-helper
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.. literalinclude:: /code_examples/synth_flow/proc_02.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/proc_02.v``
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.. literalinclude:: /code_examples/synth_flow/proc_02.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/proc_02.ys``
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.. figure:: /_images/code_examples/synth_flow/proc_03.*
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:class: width-helper
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.. literalinclude:: /code_examples/synth_flow/proc_03.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/proc_03.ys``
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.. literalinclude:: /code_examples/synth_flow/proc_03.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/proc_03.v``
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