mirror of https://github.com/YosysHQ/yosys.git
241 lines
6.9 KiB
C++
241 lines
6.9 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Dff2dffeWorker
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{
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RTLIL::Module *module;
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SigMap sigmap;
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CellTypes ct;
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typedef std::pair<RTLIL::Cell*, int> cell_int_t;
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std::map<RTLIL::SigBit, cell_int_t> bit2mux;
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std::vector<RTLIL::Cell*> dff_cells;
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std::map<RTLIL::SigBit, int> bitusers;
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typedef std::map<RTLIL::SigBit, bool> pattern_t;
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typedef std::set<pattern_t> patterns_t;
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Dff2dffeWorker(RTLIL::Module *module) : module(module), sigmap(module), ct(module->design)
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{
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for (auto wire : module->wires()) {
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if (wire->port_output)
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for (auto bit : sigmap(wire))
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bitusers[bit]++;
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}
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for (auto cell : module->cells()) {
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if (cell->type == "$mux" || cell->type == "$pmux") {
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RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
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for (int i = 0; i < GetSize(sig_y); i++)
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bit2mux[sig_y[i]] = cell_int_t(cell, i);
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}
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if (cell->type == "$dff")
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dff_cells.push_back(cell);
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for (auto conn : cell->connections()) {
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if (ct.cell_output(cell->type, conn.first))
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continue;
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for (auto bit : sigmap(conn.second))
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bitusers[bit]++;
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}
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}
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}
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patterns_t find_muxtree_feedback_patterns(RTLIL::SigBit d, RTLIL::SigBit q, pattern_t path)
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{
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patterns_t ret;
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if (d == q) {
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ret.insert(path);
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return ret;
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}
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if (bit2mux.count(d) == 0 || bitusers[d] > 1)
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return ret;
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cell_int_t mux_cell_int = bit2mux.at(d);
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RTLIL::SigSpec sig_a = sigmap(mux_cell_int.first->getPort("\\A"));
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RTLIL::SigSpec sig_b = sigmap(mux_cell_int.first->getPort("\\B"));
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RTLIL::SigSpec sig_s = sigmap(mux_cell_int.first->getPort("\\S"));
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int width = GetSize(sig_a), index = mux_cell_int.second;
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for (int i = 0; i < GetSize(sig_s); i++)
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if (path.count(sig_s[i]) && path.at(sig_s[i]))
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{
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ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path);
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if (sig_b[i*width + index] == q) {
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RTLIL::SigSpec s = mux_cell_int.first->getPort("\\B");
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s[i*width + index] = RTLIL::Sx;
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mux_cell_int.first->setPort("\\B", s);
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}
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return ret;
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}
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pattern_t path_else = path;
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for (int i = 0; i < GetSize(sig_s); i++)
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{
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if (path.count(sig_s[i]))
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continue;
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pattern_t path_this = path;
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path_else[sig_s[i]] = false;
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path_this[sig_s[i]] = true;
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for (auto &pat : find_muxtree_feedback_patterns(sig_b[i*width + index], q, path_this))
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ret.insert(pat);
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if (sig_b[i*width + index] == q) {
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RTLIL::SigSpec s = mux_cell_int.first->getPort("\\B");
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s[i*width + index] = RTLIL::Sx;
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mux_cell_int.first->setPort("\\B", s);
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}
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}
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for (auto &pat : find_muxtree_feedback_patterns(sig_a[index], q, path_else))
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ret.insert(pat);
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if (sig_a[index] == q) {
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RTLIL::SigSpec s = mux_cell_int.first->getPort("\\A");
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s[index] = RTLIL::Sx;
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mux_cell_int.first->setPort("\\A", s);
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}
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return ret;
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}
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void simplify_patterns(patterns_t&)
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{
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// TBD
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}
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RTLIL::SigSpec make_patterns_logic(patterns_t patterns)
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{
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RTLIL::SigSpec or_input;
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for (auto pat : patterns) {
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RTLIL::SigSpec s1, s2;
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for (auto it : pat) {
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s1.append(it.first);
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s2.append(it.second);
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}
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or_input.append(module->Ne(NEW_ID, s1, s2));
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}
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if (GetSize(or_input) == 0)
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return RTLIL::S1;
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if (GetSize(or_input) == 1)
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return or_input;
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return module->ReduceOr(NEW_ID, or_input);
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}
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void handle_dff_cell(RTLIL::Cell *dff_cell)
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{
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RTLIL::SigSpec sig_d = sigmap(dff_cell->getPort("\\D"));
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RTLIL::SigSpec sig_q = sigmap(dff_cell->getPort("\\Q"));
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std::map<patterns_t, std::set<int>> grouped_patterns;
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std::set<int> remaining_indices;
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for (int i = 0 ; i < GetSize(sig_d); i++) {
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patterns_t patterns = find_muxtree_feedback_patterns(sig_d[i], sig_q[i], pattern_t());
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if (!patterns.empty()) {
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simplify_patterns(patterns);
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grouped_patterns[patterns].insert(i);
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} else
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remaining_indices.insert(i);
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}
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for (auto &it : grouped_patterns) {
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RTLIL::SigSpec new_sig_d, new_sig_q;
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for (int i : it.second) {
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new_sig_d.append(sig_d[i]);
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new_sig_q.append(sig_q[i]);
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}
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RTLIL::Cell *new_cell = module->addDffe(NEW_ID, dff_cell->getPort("\\CLK"), make_patterns_logic(it.first),
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new_sig_d, new_sig_q, dff_cell->getParam("\\CLK_POLARITY").as_bool(), true);
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log(" created $dffe cell %s for %s -> %s.\n", log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q));
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}
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if (remaining_indices.empty()) {
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log(" removing now obsolete cell %s.\n", log_id(dff_cell));
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module->remove(dff_cell);
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} else if (GetSize(remaining_indices) != GetSize(sig_d)) {
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log(" removing %d now obsolete bits from cell %s.\n", GetSize(sig_d) - GetSize(remaining_indices), log_id(dff_cell));
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RTLIL::SigSpec new_sig_d, new_sig_q;
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for (int i : remaining_indices) {
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new_sig_d.append(sig_d[i]);
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new_sig_q.append(sig_q[i]);
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}
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dff_cell->setPort("\\D", new_sig_d);
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dff_cell->setPort("\\Q", new_sig_q);
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dff_cell->setParam("\\WIDTH", GetSize(remaining_indices));
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}
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}
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void run()
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{
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log("Transforming $dff to $dffe cells in module %s:\n", log_id(module));
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for (auto dff_cell : dff_cells)
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handle_dff_cell(dff_cell);
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}
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};
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struct Dff2dffePass : public Pass {
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Dff2dffePass() : Pass("dff2dffe", "transform $dff cells to $dffe cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" dff2dffe [selection]\n");
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log("\n");
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log("This pass transforms $dff cells driven by a tree of multiplexers with one or\n");
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log("more feedback paths to $dffe cells.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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// if (args[argidx] == "-foobar") {
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// foobar_mode = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto mod : design->selected_modules())
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if (!mod->has_processes_warn()) {
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Dff2dffeWorker worker(mod);
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worker.run();
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}
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}
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} Dff2dffePass;
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PRIVATE_NAMESPACE_END
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