mirror of https://github.com/YosysHQ/yosys.git
588 lines
13 KiB
Plaintext
588 lines
13 KiB
Plaintext
pattern xilinx_dsp_pack
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state <SigBit> clock
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state <SigSpec> sigA sigB sigC sigD sigM sigP
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state <IdString> postAddAB postAddMuxAB
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state <bool> ffA1cepol ffA2cepol ffADcepol ffB1cepol ffB2cepol ffDcepol ffMcepol ffPcepol
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state <bool> ffArstpol ffADrstpol ffBrstpol ffDrstpol ffMrstpol ffPrstpol
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state <Cell*> ffAD ffADcemux ffADrstmux ffA1 ffA1cemux ffA1rstmux ffA2 ffA2cemux ffA2rstmux
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state <Cell*> ffB1 ffB1cemux ffB1rstmux ffB2 ffB2cemux ffB2rstmux
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state <Cell*> ffD ffDcemux ffDrstmux ffM ffMcemux ffMrstmux ffP ffPcemux ffPrstmux
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// subpattern
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state <SigSpec> argQ argD
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state <bool> ffcepol ffrstpol
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state <int> ffoffset
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff dffcemux dffrstmux
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udata <bool> dffcepol dffrstpol
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match dsp
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select dsp->type.in(\DSP48E1)
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endmatch
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code sigA sigB sigC sigD sigM clock
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auto unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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sigA = unextend(port(dsp, \A));
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sigB = unextend(port(dsp, \B));
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sigC = port(dsp, \C, SigSpec());
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sigD = port(dsp, \D, SigSpec());
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SigSpec P = port(dsp, \P);
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if (param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") {
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// Only care about those bits that are used
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int i;
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for (i = 0; i < GetSize(P); i++) {
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if (nusers(P[i]) <= 1)
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break;
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sigM.append(P[i]);
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}
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log_assert(nusers(P.extract_end(i)) <= 1);
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}
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else
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sigM = P;
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// This sigM could have no users if downstream $add
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// is narrower than $mul result, for example
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if (sigM.empty())
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reject;
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clock = port(dsp, \CLK, SigBit());
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endcode
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code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock
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if (param(dsp, \ADREG).as_int() == 0) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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ffAD = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffADrstmux = dffrstmux;
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ffADrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffADcemux = dffcemux;
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ffADcepol = dffcepol;
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}
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sigA = dffD;
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}
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}
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endcode
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match preAdd
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if sigD.empty() || sigD.is_fully_zero()
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// Ensure that preAdder not already used
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if param(dsp, \USE_DPORT, Const("FALSE")).decode_string() == "FALSE"
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if port(dsp, \INMODE, Const(0, 5)).is_fully_zero()
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select preAdd->type.in($add)
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// Output has to be 25 bits or less
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select GetSize(port(preAdd, \Y)) <= 25
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select nusers(port(preAdd, \Y)) == 2
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choice <IdString> AB {\A, \B}
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// A port has to be 30 bits or less
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select GetSize(port(preAdd, AB)) <= 30
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define <IdString> BA (AB == \A ? \B : \A)
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// D port has to be 25 bits or less
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select GetSize(port(preAdd, BA)) <= 25
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index <SigSpec> port(preAdd, \Y) === sigA
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optional
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endmatch
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code sigA sigD
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if (preAdd) {
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sigA = port(preAdd, \A);
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sigD = port(preAdd, \B);
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if (GetSize(sigA) < GetSize(sigD))
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std::swap(sigA, sigD);
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}
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endcode
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code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock ffA2 ffA2cemux ffA2rstmux ffA2cepol ffArstpol ffA1 ffA1cemux ffA1rstmux ffA1cepol
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// Only search for ffA2 if there was a pre-adder
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// (otherwise ffA2 would have been matched as ffAD)
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if (preAdd) {
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if (param(dsp, \AREG).as_int() == 0) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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ffA2 = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffA2rstmux = dffrstmux;
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ffArstpol = dffrstpol;
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}
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if (dffcemux) {
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ffA2cepol = dffcepol;
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ffA2cemux = dffcemux;
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}
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sigA = dffD;
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}
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}
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}
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// And if there wasn't a pre-adder,
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// move AD register to A
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else if (ffAD) {
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log_assert(!ffA2 && !ffA2cemux && !ffA2rstmux);
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std::swap(ffA2, ffAD);
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std::swap(ffA2cemux, ffADcemux);
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std::swap(ffA2rstmux, ffADrstmux);
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ffA2cepol = ffADcepol;
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ffArstpol = ffADrstpol;
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}
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// Now attempt to match A1
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if (ffA2) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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if ((ffA2rstmux != nullptr) ^ (dffrstmux != nullptr))
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goto ffA1_end;
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if (dffrstmux) {
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if (ffArstpol != dffrstpol)
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goto ffA1_end;
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if (port(ffA2rstmux, \S) != port(dffrstmux, \S))
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goto ffA1_end;
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ffA1rstmux = dffrstmux;
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}
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ffA1 = dff;
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clock = dffclock;
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if (dffcemux) {
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ffA1cemux = dffcemux;
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ffA1cepol = dffcepol;
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}
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sigA = dffD;
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ffA1_end: ;
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}
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}
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endcode
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code argQ ffB2 ffB2cemux ffB2rstmux ffB2cepol ffBrstpol sigB clock ffB1 ffB1cemux ffB1rstmux ffB1cepol
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if (param(dsp, \BREG).as_int() == 0) {
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argQ = sigB;
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subpattern(in_dffe);
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if (dff) {
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ffB2 = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffB2rstmux = dffrstmux;
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ffBrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffB2cemux = dffcemux;
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ffB2cepol = dffcepol;
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}
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sigB = dffD;
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// Now attempt to match B1
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if (ffB2) {
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argQ = sigB;
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subpattern(in_dffe);
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if (dff) {
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if ((ffB2rstmux != nullptr) ^ (dffrstmux != nullptr))
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goto ffB1_end;
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if (dffrstmux) {
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if (ffBrstpol != dffrstpol)
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goto ffB1_end;
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if (port(ffB2rstmux, \S) != port(dffrstmux, \S))
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goto ffB1_end;
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ffB1rstmux = dffrstmux;
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}
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ffB1 = dff;
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clock = dffclock;
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if (dffcemux) {
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ffB1cemux = dffcemux;
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ffB1cepol = dffcepol;
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}
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sigB = dffD;
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ffB1_end: ;
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}
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}
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}
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}
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endcode
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code argQ ffD ffDcemux ffDrstmux ffDcepol ffDrstpol sigD clock
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if (param(dsp, \DREG).as_int() == 0) {
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argQ = sigD;
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subpattern(in_dffe);
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if (dff) {
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ffD = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffDrstmux = dffrstmux;
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ffDrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffDcemux = dffcemux;
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ffDcepol = dffcepol;
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}
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sigD = dffD;
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}
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}
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endcode
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code argD ffM ffMcemux ffMrstmux ffMcepol ffMrstpol sigM sigP clock
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if (param(dsp, \MREG).as_int() == 0 && nusers(sigM) == 2) {
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argD = sigM;
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subpattern(out_dffe);
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if (dff) {
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ffM = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffMrstmux = dffrstmux;
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ffMrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffMcemux = dffcemux;
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ffMcepol = dffcepol;
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}
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sigM = dffQ;
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}
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}
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sigP = sigM;
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endcode
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match postAdd
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// Ensure that Z mux is not already used
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if port(dsp, \OPMODE, SigSpec()).extract(4,3).is_fully_zero()
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select postAdd->type.in($add)
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select GetSize(port(postAdd, \Y)) <= 48
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choice <IdString> AB {\A, \B}
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select nusers(port(postAdd, AB)) <= 3
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filter ffMcemux || nusers(port(postAdd, AB)) == 2
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filter !ffMcemux || nusers(port(postAdd, AB)) == 3
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index <SigBit> port(postAdd, AB)[0] === sigP[0]
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filter GetSize(port(postAdd, AB)) >= GetSize(sigP)
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filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP
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filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(sigP[GetSize(sigP)-1], GetSize(port(postAdd, AB))-GetSize(sigP))
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set postAddAB AB
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optional
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endmatch
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code sigC sigP
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if (postAdd) {
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sigC = port(postAdd, postAddAB == \A ? \B : \A);
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sigP = port(postAdd, \Y);
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}
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endcode
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code argD ffP ffPcemux ffPrstmux ffPcepol ffPrstpol sigP clock
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if (param(dsp, \PREG).as_int() == 0) {
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int users = 2;
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// If ffMcemux and no postAdd new-value net must have three users: ffMcemux, ffM and ffPcemux
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if (ffMcemux && !postAdd) users++;
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if (nusers(sigP) == users) {
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argD = sigP;
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subpattern(out_dffe);
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if (dff) {
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ffP = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffPrstmux = dffrstmux;
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ffPrstpol = dffrstpol;
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}
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if (dffcemux) {
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ffPcemux = dffcemux;
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ffPcepol = dffcepol;
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}
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sigP = dffQ;
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}
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}
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}
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endcode
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match postAddMux
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if postAdd
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if ffP
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select postAddMux->type.in($mux)
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select nusers(port(postAddMux, \Y)) == 2
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(postAddMux, AB) === sigP
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index <SigSpec> port(postAddMux, \Y) === sigC
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set postAddMuxAB AB
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optional
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endmatch
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code sigC
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if (postAddMux)
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sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A);
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endcode
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match overflow
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if ffP
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if param(dsp, \USE_PATTERN_DETECT, Const("NO_PATDET")).decode_string() == "NO_PATDET"
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select overflow->type.in($ge)
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select GetSize(port(overflow, \Y)) <= 48
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select port(overflow, \B).is_fully_const()
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define <Const> B port(overflow, \B).as_const()
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select std::count(B.bits.begin(), B.bits.end(), State::S1) == 1
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index <SigSpec> port(overflow, \A) === sigP
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optional
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endmatch
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code
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accept;
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endcode
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// #######################
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subpattern in_dffe
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arg argD argQ clock
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code
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dff = nullptr;
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for (auto c : argQ.chunks()) {
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if (!c.wire)
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reject;
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if (c.wire->get_bool_attribute(\keep))
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reject;
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Const init = c.wire->attributes.at(\init, State::Sx);
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if (!init.is_fully_undef() && !init.is_fully_zero())
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reject;
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}
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endcode
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match ff
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select ff->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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slice offset GetSize(port(ff, \D))
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index <SigBit> port(ff, \Q)[offset] === argQ[0]
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// Check that the rest of argQ is present
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filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
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filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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set ffoffset offset
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endmatch
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code argQ argD
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{
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if (clock != SigBit() && port(ff, \CLK) != clock)
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reject;
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SigSpec Q = port(ff, \Q);
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dff = ff;
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dffclock = port(ff, \CLK);
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dffD = argQ;
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argD = port(ff, \D);
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argQ = Q;
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dffD.replace(argQ, argD);
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// Only search for ffrstmux if dffD only
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// has two (ff, ffrstmux) users
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if (nusers(dffD) > 2)
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argD = SigSpec();
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}
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endcode
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match ffrstmux
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if !argD.empty()
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select ffrstmux->type.in($mux)
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index <SigSpec> port(ffrstmux, \Y) === argD
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choice <IdString> BA {\B, \A}
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// DSP48E1 only supports reset to zero
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select port(ffrstmux, BA).is_fully_zero()
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define <bool> pol (BA == \B)
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set ffrstpol pol
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semioptional
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endmatch
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code argD
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if (ffrstmux) {
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dffrstmux = ffrstmux;
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dffrstpol = ffrstpol;
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argD = port(ffrstmux, ffrstpol ? \A : \B);
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dffD.replace(port(ffrstmux, \Y), argD);
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// Only search for ffcemux if argQ has at
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// least 3 users (ff, <upstream>, ffrstmux) and
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// dffD only has two (ff, ffrstmux)
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if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
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argD = SigSpec();
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}
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else
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dffrstmux = nullptr;
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endcode
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match ffcemux
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if !argD.empty()
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select ffcemux->type.in($mux)
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index <SigSpec> port(ffcemux, \Y) === argD
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(ffcemux, AB) === argQ
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define <bool> pol (AB == \A)
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set ffcepol pol
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semioptional
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endmatch
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code argD
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if (ffcemux) {
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dffcemux = ffcemux;
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dffcepol = ffcepol;
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argD = port(ffcemux, ffcepol ? \B : \A);
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dffD.replace(port(ffcemux, \Y), argD);
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}
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else
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dffcemux = nullptr;
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endcode
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// #######################
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subpattern out_dffe
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arg argD argQ clock
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code
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dff = nullptr;
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for (auto c : argD.chunks())
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if (c.wire->get_bool_attribute(\keep))
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reject;
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endcode
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match ffcemux
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select ffcemux->type.in($mux)
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// ffcemux output must have two users: ffcemux and ff.D
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select nusers(port(ffcemux, \Y)) == 2
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choice <IdString> AB {\A, \B}
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// keep-last-value net must have at least three users: ffcemux, ff, downstream sink(s)
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select nusers(port(ffcemux, AB)) >= 3
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slice offset GetSize(port(ffcemux, \Y))
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define <IdString> BA (AB == \A ? \B : \A)
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index <SigBit> port(ffcemux, BA)[offset] === argD[0]
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// Check that the rest of argD is present
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filter GetSize(port(ffcemux, BA)) >= offset + GetSize(argD)
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filter port(ffcemux, BA).extract(offset, GetSize(argD)) == argD
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set ffoffset offset
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define <bool> pol (AB == \A)
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set ffcepol pol
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semioptional
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endmatch
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code argD argQ
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dffcemux = ffcemux;
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if (ffcemux) {
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SigSpec BA = port(ffcemux, ffcepol ? \B : \A);
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SigSpec Y = port(ffcemux, \Y);
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argQ = argD;
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argD.replace(BA, Y);
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argQ.replace(BA, port(ffcemux, ffcepol ? \A : \B));
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dffcemux = ffcemux;
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dffcepol = ffcepol;
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}
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endcode
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match ffrstmux
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select ffrstmux->type.in($mux)
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// ffrstmux output must have two users: ffrstmux and ff.D
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select nusers(port(ffrstmux, \Y)) == 2
|
|
|
|
choice <IdString> BA {\B, \A}
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|
// DSP48E1 only supports reset to zero
|
|
select port(ffrstmux, BA).is_fully_zero()
|
|
|
|
slice offset GetSize(port(ffrstmux, \Y))
|
|
define <IdString> AB (BA == \B ? \A : \B)
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index <SigBit> port(ffrstmux, AB)[offset] === argD[0]
|
|
|
|
// Check that offset is consistent
|
|
filter !ffcemux || ffoffset == offset
|
|
// Check that the rest of argD is present
|
|
filter GetSize(port(ffrstmux, AB)) >= offset + GetSize(argD)
|
|
filter port(ffrstmux, AB).extract(offset, GetSize(argD)) == argD
|
|
|
|
set ffoffset offset
|
|
define <bool> pol (AB == \A)
|
|
set ffrstpol pol
|
|
|
|
semioptional
|
|
endmatch
|
|
|
|
code argD argQ
|
|
dffrstmux = ffrstmux;
|
|
if (ffrstmux) {
|
|
SigSpec AB = port(ffrstmux, ffrstpol ? \A : \B);
|
|
SigSpec Y = port(ffrstmux, \Y);
|
|
argD.replace(AB, Y);
|
|
|
|
dffrstmux = ffrstmux;
|
|
dffrstpol = ffrstpol;
|
|
}
|
|
endcode
|
|
|
|
match ff
|
|
select ff->type.in($dff)
|
|
// DSP48E1 does not support clock inversion
|
|
select param(ff, \CLK_POLARITY).as_bool()
|
|
|
|
slice offset GetSize(port(ff, \D))
|
|
index <SigBit> port(ff, \D)[offset] === argD[0]
|
|
|
|
// Check that offset is consistent
|
|
filter (!ffcemux && !ffrstmux) || ffoffset == offset
|
|
// Check that the rest of argD is present
|
|
filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
|
|
filter port(ff, \D).extract(offset, GetSize(argD)) == argD
|
|
// Check that FF.Q is connected to CE-mux
|
|
filter !ffcemux || port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
|
|
|
|
set ffoffset offset
|
|
endmatch
|
|
|
|
code argQ
|
|
if (ff) {
|
|
if (clock != SigBit() && port(ff, \CLK) != clock)
|
|
reject;
|
|
|
|
SigSpec D = port(ff, \D);
|
|
SigSpec Q = port(ff, \Q);
|
|
if (!ffcemux) {
|
|
argQ = argD;
|
|
argQ.replace(D, Q);
|
|
}
|
|
|
|
for (auto c : argQ.chunks()) {
|
|
Const init = c.wire->attributes.at(\init, State::Sx);
|
|
if (!init.is_fully_undef() && !init.is_fully_zero())
|
|
reject;
|
|
}
|
|
|
|
dff = ff;
|
|
dffQ = argQ;
|
|
dffclock = port(ff, \CLK);
|
|
}
|
|
// No enable/reset mux possible without flop
|
|
else if (dffcemux || dffrstmux)
|
|
reject;
|
|
endcode
|