mirror of https://github.com/YosysHQ/yosys.git
121 lines
3.2 KiB
Verilog
121 lines
3.2 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// ============================================================================
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module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
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assign Y = A;
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endmodule
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module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
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assign Y = A;
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endmodule
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module \$__ABC_RAM32X1D (
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output DPO, SPO,
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input D,
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input WCLK,
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input WE,
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input A0, A1, A2, A3, A4,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
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);
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parameter INIT = 32'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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RAM32X1D #(
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.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
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) _TECHMAP_REPLACE_ (
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.DPO(DPO), .SPO(SPO),
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.D(D), .WCLK(WCLK), .WE(WE),
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.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
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.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
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);
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endmodule
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module \$__ABC_RAM64X1D (
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output DPO, SPO,
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input D,
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input WCLK,
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input WE,
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input A0, A1, A2, A3, A4, A5,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
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);
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parameter INIT = 64'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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RAM64X1D #(
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.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
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) _TECHMAP_REPLACE_ (
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.DPO(DPO), .SPO(SPO),
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.D(D), .WCLK(WCLK), .WE(WE),
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.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
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.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
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);
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endmodule
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module \$__ABC_RAM128X1D (
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output DPO, SPO,
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input D,
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input WCLK,
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input WE,
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input A,
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input DPRA,
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);
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parameter INIT = 128'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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RAM128X1D #(
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.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
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) _TECHMAP_REPLACE_ (
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.DPO(DPO), .SPO(SPO),
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.D(D), .WCLK(WCLK), .WE(WE),
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.A(A),
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.DPRA(DPRA)
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);
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endmodule
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module \$__ABC_SRL16E (
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output Q,
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input A0, A1, A2, A3, CE, CLK, D
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);
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parameter [15:0] INIT = 16'h0000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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SRL16E #(
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.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
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) _TECHMAP_REPLACE_ (
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.Q(Q),
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.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
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);
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endmodule
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module \$__ABC_SRLC32E (
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output Q,
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output Q31,
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input [4:0] A,
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input CE, CLK, D
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);
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parameter [31:0] INIT = 32'h00000000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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SRLC32E #(
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.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
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) _TECHMAP_REPLACE_ (
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.Q(Q), .Q31(Q31),
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.A(A), .CE(CE), .CLK(CLK), .D(D)
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);
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endmodule
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