mirror of https://github.com/YosysHQ/yosys.git
21 lines
761 B
Python
21 lines
761 B
Python
import os
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from pyosys import libyosys as ys
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__dir__ = os.path.dirname(os.path.abspath(__file__))
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add_sub = os.path.join(__dir__, "..", "common", "add_sub.v")
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base = ys.Design()
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ys.run_pass(f"read_verilog {add_sub}", base)
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ys.run_pass("hierarchy -top top", base)
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ys.run_pass("proc", base)
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ys.run_pass("equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5", base)
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postopt = ys.Design()
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ys.run_pass("design -load postopt", postopt)
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ys.run_pass("cd top", postopt)
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ys.run_pass("select -assert-min 25 t:LUT4", postopt)
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ys.run_pass("select -assert-max 26 t:LUT4", postopt)
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ys.run_pass("select -assert-count 10 t:PFUMX", postopt)
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ys.run_pass("select -assert-count 6 t:L6MUX21", postopt)
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ys.run_pass("select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D", postopt)
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