mirror of https://github.com/YosysHQ/yosys.git
344 lines
10 KiB
C++
344 lines
10 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include <string.h>
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#include <dirent.h>
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#undef CLUSTER_CELLS_AND_PORTBOXES
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struct ShowWorker
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{
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CellTypes ct;
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std::vector<std::string> dot_escape_store;
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std::map<RTLIL::IdString, int> dot_id2num_store;
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std::map<RTLIL::IdString, int> autonames;
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int single_idx_count;
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struct net_conn { std::set<std::string> in, out; };
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std::map<std::string, net_conn> net_conn_map;
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FILE *f;
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RTLIL::Design *design;
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RTLIL::Module *module;
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int page_counter;
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const char *escape(std::string id, bool is_name = false)
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{
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if (id.size() == 0)
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return "";
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if (id[0] == '$' && is_name) {
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if (autonames.count(id) == 0) {
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autonames[id] = autonames.size() + 1;
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log("Generated short name for internal identifier: _%d_ -> %s\n", autonames[id], id.c_str());
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}
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id = stringf("_%d_", autonames[id]);
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}
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if (id[0] == '\\')
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id = id.substr(1);
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std::string str;
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for (char ch : id) {
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if (ch == '\\' || ch == '"')
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str += "\\";
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str += ch;
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}
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dot_escape_store.push_back(str);
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return dot_escape_store.back().c_str();
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}
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int id2num(RTLIL::IdString id)
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{
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if (dot_id2num_store.count(id) > 0)
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return dot_id2num_store[id];
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return dot_id2num_store[id] = dot_id2num_store.size() + 1;
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}
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std::string gen_signode_simple(RTLIL::SigSpec sig, bool range_check = true)
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{
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sig.optimize();
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if (sig.chunks.size() == 0) {
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fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count);
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return stringf("v%d", single_idx_count++);
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}
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if (sig.chunks.size() == 1) {
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RTLIL::SigChunk &c = sig.chunks[0];
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if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) {
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if (!range_check || c.wire->width == c.width)
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return stringf("n%d", id2num(c.wire->name));
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} else {
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fprintf(f, "v%d [ label=\"%s\" ];\n", single_idx_count, escape(log_signal(c), true));
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return stringf("v%d", single_idx_count++);
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}
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}
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return std::string();
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}
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std::string gen_portbox(std::string port, RTLIL::SigSpec sig, bool driver, std::string *node = NULL)
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{
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std::string code;
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std::string net = gen_signode_simple(sig);
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if (net.empty())
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{
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std::string label_string;
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sig.optimize();
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int pos = sig.width-1;
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int idx = single_idx_count++;
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for (int i = int(sig.chunks.size())-1; i >= 0; i--) {
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RTLIL::SigChunk &c = sig.chunks[i];
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net = gen_signode_simple(c, false);
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assert(!net.empty());
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if (driver) {
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label_string += stringf("<s%d> %d:%d - %d:%d |", i, pos, pos-c.width+1, c.offset+c.width-1, c.offset);
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net_conn_map[net].in.insert(stringf("x%d:s%d", idx, i));
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} else {
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label_string += stringf("<s%d> %d:%d - %d:%d |", i, c.offset+c.width-1, c.offset, pos, pos-c.width+1);
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net_conn_map[net].out.insert(stringf("x%d:s%d", idx, i));
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}
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pos -= c.width;
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}
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if (label_string[label_string.size()-1] == '|')
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label_string = label_string.substr(0, label_string.size()-1);
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code += stringf("x%d [ shape=record, style=rounded, label=\"%s\" ];\n", idx, label_string.c_str());
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if (!port.empty()) {
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if (driver)
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code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both];\n", port.c_str(), idx);
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else
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code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both];\n", idx, port.c_str());
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}
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if (node != NULL)
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*node = stringf("x%d", idx);
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}
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else
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{
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if (!port.empty()) {
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if (driver)
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net_conn_map[net].in.insert(port);
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else
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net_conn_map[net].out.insert(port);
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}
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if (node != NULL)
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*node = net;
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}
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return code;
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}
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void handle_module()
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{
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single_idx_count = 0;
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dot_escape_store.clear();
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dot_id2num_store.clear();
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net_conn_map.clear();
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fprintf(f, "digraph \"%s\" {\n", escape(module->name));
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fprintf(f, "rankdir=\"LR\";\n");
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fprintf(f, "remincross=true;\n");
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std::map<std::string, std::string> wires_on_demand;
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for (auto &it : module->wires) {
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if (!design->selected_member(module->name, it.first))
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continue;
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const char *shape = "diamond";
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if (it.second->port_input || it.second->port_output)
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shape = "octagon";
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if (it.first[0] == '\\')
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fprintf(f, "n%d [ shape=%s, label=\"%s\" ];\n",
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id2num(it.first), shape, escape(it.first));
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else {
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wires_on_demand[stringf("n%d", id2num(it.first))] = it.first;
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}
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}
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for (auto &it : module->cells)
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{
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if (!design->selected_member(module->name, it.first))
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continue;
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std::vector<RTLIL::IdString> in_ports, out_ports;
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for (auto &conn : it.second->connections) {
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if (ct.cell_input(it.second->type, conn.first))
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in_ports.push_back(conn.first);
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else
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out_ports.push_back(conn.first);
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}
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std::string label_string = "{{";
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for (auto &p : in_ports)
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label_string += stringf("<p%d> %s|", id2num(p), escape(p));
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if (label_string[label_string.size()-1] == '|')
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label_string = label_string.substr(0, label_string.size()-1);
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label_string += stringf("}|%s\\n%s|{", escape(it.first, true), escape(it.second->type));
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for (auto &p : out_ports)
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label_string += stringf("<p%d> %s|", id2num(p), escape(p));
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if (label_string[label_string.size()-1] == '|')
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label_string = label_string.substr(0, label_string.size()-1);
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label_string += "}}";
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std::string code;
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for (auto &conn : it.second->connections) {
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code += gen_portbox(stringf("c%d:p%d", id2num(it.first), id2num(conn.first)),
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conn.second, !ct.cell_input(it.second->type, conn.first));
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}
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#ifdef CLUSTER_CELLS_AND_PORTBOXES
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if (!code.empty())
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fprintf(f, "subgraph cluster_c%d {\nc%d [ shape=record, label=\"%s\" ];\n%s}\n",
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id2num(it.first), id2num(it.first), label_string.c_str(), code.c_str());
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else
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#endif
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fprintf(f, "c%d [ shape=record, label=\"%s\" ];\n%s",
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id2num(it.first), label_string.c_str(), code.c_str());
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}
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for (auto &conn : module->connections)
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{
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bool found_lhs_wire = false;
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for (auto &c : conn.first.chunks) {
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if (c.wire != NULL && design->selected_member(module->name, c.wire->name))
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found_lhs_wire = true;
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}
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bool found_rhs_wire = false;
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for (auto &c : conn.second.chunks) {
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if (c.wire != NULL && design->selected_member(module->name, c.wire->name))
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found_rhs_wire = true;
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}
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if (!found_lhs_wire || !found_rhs_wire)
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continue;
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std::string code, left_node, right_node;
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code += gen_portbox("", conn.second, false, &left_node);
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code += gen_portbox("", conn.first, true, &right_node);
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fprintf(f, "%s", code.c_str());
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if (left_node[0] == 'x' && right_node[0] == 'x')
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fprintf(f, "%s:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both];\n", left_node.c_str(), right_node.c_str());
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else if (left_node[0] == 'x')
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net_conn_map[right_node].in.insert(left_node);
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else if (right_node[0] == 'x')
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net_conn_map[left_node].out.insert(right_node);
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else {
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net_conn_map[right_node].in.insert(stringf("x%d:e", single_idx_count));
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net_conn_map[left_node].out.insert(stringf("x%d:w", single_idx_count));
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fprintf(f, "x%d [shape=box, style=rounded, label=\"BUF\"];\n", single_idx_count++);
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}
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}
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for (auto &it : net_conn_map)
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{
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if (wires_on_demand.count(it.first) > 0) {
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if (it.second.in.size() == 1 && it.second.out.size() == 1) {
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fprintf(f, "%s:e -> %s:w;\n", it.second.in.begin()->c_str(), it.second.out.begin()->c_str());
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continue;
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}
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if (it.second.in.size() == 0 || it.second.out.size() == 0)
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fprintf(f, "%s [ shape=diamond, label=\"%s\" ];\n", it.first.c_str(), escape(wires_on_demand[it.first], true));
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else
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fprintf(f, "%s [ shape=point ];\n", it.first.c_str());
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}
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for (auto &it2 : it.second.in)
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fprintf(f, "%s:e -> %s:w;\n", it2.c_str(), it.first.c_str());
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for (auto &it2 : it.second.out)
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fprintf(f, "%s:e -> %s:w;\n", it.first.c_str(), it2.c_str());
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}
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fprintf(f, "};\n");
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}
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ShowWorker(FILE *f, RTLIL::Design *design) : f(f), design(design)
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{
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ct.setup_internals();
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ct.setup_internals_mem();
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ct.setup_stdcells();
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ct.setup_stdcells_mem();
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design->optimize();
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page_counter = 0;
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for (auto &mod_it : design->modules)
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{
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module = mod_it.second;
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if (!design->selected_module(module->name))
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continue;
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if (design->selected_whole_module(module->name))
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log("Dumping module %s to page %d.\n", module->name.c_str(), ++page_counter);
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else
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log("Dumping selected parts of module %s to page %d.\n", module->name.c_str(), ++page_counter);
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handle_module();
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}
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}
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};
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struct ShowPass : public Pass {
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ShowPass() : Pass("show") { }
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Generating Graphviz representation of design.\n");
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std::string viewer_exe;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-viewer" && argidx+1 < args.size()) {
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viewer_exe = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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log("Writing dot description to `yosys-show.dot'.\n");
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FILE *f = fopen("yosys-show.dot", "w");
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if (f == NULL)
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log_cmd_error("Can't open dot file `yosys-show.dot' for writing.\n");
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ShowWorker worker(f, design);
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fclose(f);
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if (worker.page_counter == 0)
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log_cmd_error("Nothing there to show.\n");
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std::string cmd = stringf("dot -Tps -o yosys-show.ps yosys-show.dot");
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log("Exec: %s\n", cmd.c_str());
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if (system(cmd.c_str()) != 0)
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log_cmd_error("Shell command failed!\n");
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if (!viewer_exe.empty()) {
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cmd = stringf("%s yosys-show.ps &", viewer_exe.c_str());
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log("Exec: %s\n", cmd.c_str());
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if (system(cmd.c_str()) != 0)
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log_cmd_error("Shell command failed!\n");
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}
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}
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} ShowPass;
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