This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
6abf79eb28
yosys
/
manual
/
PRESENTATION_Prog
/
sigmap_test.v
4 lines
66 B
Verilog
Raw
Blame
History
module
test
(
input
a
,
output
x
,
y
)
;
assign
x
=
a
,
y
=
a
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink