mirror of https://github.com/YosysHQ/yosys.git
276 lines
7.9 KiB
C++
276 lines
7.9 KiB
C++
#include "kernel/yosys.h"
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#include "kernel/celltypes.h"
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#include "kernel/ff.h"
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#include "kernel/ffinit.h"
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#include <variant>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct EnableLogic {
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Wire* wire;
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bool pol;
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};
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void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_output, EnableLogic enable) {
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auto anyseq = mod->Anyseq(NEW_ID, mux_input.size());
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SigSpec mux_a, mux_b;
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if (enable.pol) {
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mux_a = mux_input;
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mux_b = anyseq;
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} else {
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mux_a = anyseq;
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mux_b = mux_input;
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}
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(void)mod->addMux(NEW_ID,
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mux_a,
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mux_b,
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enable.wire,
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mux_output);
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}
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bool abstract_state_port(FfData& ff, SigSpec& port_sig, std::set<int> offsets, EnableLogic enable) {
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Wire* abstracted = ff.module->addWire(NEW_ID, offsets.size());
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SigSpec mux_input;
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int abstracted_idx = 0;
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for (int d_idx = 0; d_idx < ff.width; d_idx++) {
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if (offsets.count(d_idx)) {
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mux_input.append(port_sig[d_idx]);
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port_sig[d_idx].wire = abstracted;
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port_sig[d_idx].offset = abstracted_idx;
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log_assert(abstracted_idx < abstracted->width);
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abstracted_idx++;
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}
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}
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emit_mux_anyseq(ff.module, mux_input, abstracted, enable);
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(void)ff.emit();
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return true;
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}
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using SelReason=std::variant<Wire*, Cell*>;
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dict<SigBit, std::vector<SelReason>> gather_selected_reps(Module* mod, SigMap& sigmap) {
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dict<SigBit, std::vector<SelReason>> selected_reps;
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// Collect reps for all wire bits of selected wires
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for (auto wire : mod->selected_wires())
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for (auto bit : sigmap(wire))
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selected_reps.insert(bit).first->second.push_back(wire);
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// Collect reps for all output wire bits of selected cells
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for (auto cell : mod->selected_cells())
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for (auto conn : cell->connections())
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if (cell->output(conn.first))
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for (auto bit : conn.second.bits())
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selected_reps.insert(sigmap(bit)).first->second.push_back(cell);
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return selected_reps;
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}
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void explain_selections(const std::vector<SelReason>& reasons) {
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for (std::variant<Wire*, Cell*> reason : reasons) {
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if (Cell** cell_reason = std::get_if<Cell*>(&reason))
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log_debug("\tcell %s\n", (*cell_reason)->name.c_str());
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else if (Wire** wire_reason = std::get_if<Wire*>(&reason))
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log_debug("\twire %s\n", (*wire_reason)->name.c_str());
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else
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log_assert(false && "insane reason variant\n");
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}
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}
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unsigned int abstract_state(Module* mod, EnableLogic enable) {
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CellTypes ct;
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ct.setup_internals_ff();
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SigMap sigmap(mod);
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dict<SigBit, std::vector<SelReason>> selected_reps = gather_selected_reps(mod, sigmap);
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unsigned int changed = 0;
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std::vector<FfData> ffs;
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// Abstract flop inputs if they're driving a selected output rep
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for (auto cell : mod->cells()) {
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if (!ct.cell_types.count(cell->type))
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continue;
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FfData ff(nullptr, cell);
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if (ff.has_sr)
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log_cmd_error("SR not supported\n");
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ffs.push_back(ff);
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}
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for (auto ff : ffs) {
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// A bit inefficient
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std::set<int> offsets_to_abstract;
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for (auto bit : ff.sig_q)
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if (selected_reps.count(sigmap(bit))) {
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log_debug("Abstracting state for bit %s due to selections:\n", log_signal(bit));
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explain_selections(selected_reps.at(sigmap(bit)));
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offsets_to_abstract.insert(bit.offset);
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}
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if (offsets_to_abstract.empty())
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continue;
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// Normalize to simpler FF
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ff.unmap_ce();
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ff.unmap_srst();
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if (ff.has_arst)
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ff.arst_to_aload();
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if (ff.has_aload)
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changed += abstract_state_port(ff, ff.sig_ad, offsets_to_abstract, enable);
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changed += abstract_state_port(ff, ff.sig_d, offsets_to_abstract, enable);
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}
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return changed;
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}
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bool abstract_value_port(Module* mod, Cell* cell, std::set<int> offsets, IdString port_name, EnableLogic enable) {
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Wire* to_abstract = mod->addWire(NEW_ID, offsets.size());
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SigSpec mux_input;
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SigSpec mux_output;
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const SigSpec& old_port = cell->getPort(port_name);
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SigSpec new_port = old_port;
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int to_abstract_idx = 0;
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for (int port_idx = 0; port_idx < old_port.size(); port_idx++) {
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if (offsets.count(port_idx)) {
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mux_output.append(old_port[port_idx]);
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SigBit in_bit {to_abstract, to_abstract_idx};
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new_port.replace(port_idx, in_bit);
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mux_input.append(in_bit);
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log_assert(to_abstract_idx < to_abstract->width);
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to_abstract_idx++;
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}
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}
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cell->setPort(port_name, new_port);
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emit_mux_anyseq(mod, mux_input, mux_output, enable);
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return true;
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}
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unsigned int abstract_value(Module* mod, EnableLogic enable) {
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SigMap sigmap(mod);
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dict<SigBit, std::vector<SelReason>> selected_reps = gather_selected_reps(mod, sigmap);
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unsigned int changed = 0;
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std::vector<Cell*> cells_snapshot = mod->cells();
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for (auto cell : cells_snapshot) {
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for (auto conn : cell->connections())
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if (cell->output(conn.first)) {
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std::set<int> offsets_to_abstract;
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for (int i = 0; i < conn.second.size(); i++) {
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if (selected_reps.count(sigmap(conn.second[i]))) {
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log_debug("Abstracting value for bit %s due to selections:\n", log_signal(conn.second[i]));
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explain_selections(selected_reps.at(sigmap(conn.second[i])));
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offsets_to_abstract.insert(i);
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}
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}
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if (offsets_to_abstract.empty())
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continue;
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changed += abstract_value_port(mod, cell, offsets_to_abstract, conn.first, enable);
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}
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}
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return changed;
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}
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unsigned int abstract_init(Module* mod) {
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unsigned int changed = 0;
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FfInitVals initvals;
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SigMap sigmap(mod);
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initvals.set(&sigmap, mod);
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for (auto wire : mod->selected_wires())
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for (auto bit : SigSpec(wire)) {
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// TODO these don't seem too informative
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log_debug("Removing init bit on %s due to selected wire %s\n", log_signal(bit), wire->name.c_str());
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initvals.remove_init(bit);
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changed++;
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}
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for (auto cell : mod->selected_cells())
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for (auto conn : cell->connections())
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if (cell->output(conn.first))
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for (auto bit : conn.second.bits()) {
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log_debug("Removing init bit on %s due to selected cell %s\n", log_signal(bit), cell->name.c_str());
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initvals.remove_init(bit);
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changed++;
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}
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return changed;
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}
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struct AbstractPass : public Pass {
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AbstractPass() : Pass("abstract", "extract clock gating out of flip flops") { }
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void help() override {
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// TODO
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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log_header(design, "Executing ABSTRACT pass.\n");
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size_t argidx;
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enum Mode {
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None,
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State,
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Initial,
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Value,
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};
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Mode mode;
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std::string enable_name;
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bool enable_pol; // true is high
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-state") {
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mode = State;
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continue;
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}
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if (arg == "-init") {
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mode = Initial;
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continue;
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}
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if (arg == "-value") {
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mode = Value;
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continue;
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}
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if (arg == "-enable") {
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enable_name = args[++argidx];
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enable_pol = true;
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continue;
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}
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if (arg == "-enablen") {
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enable_name = args[++argidx];
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enable_pol = false;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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unsigned int changed = 0;
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if ((mode == State) || (mode == Value)) {
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if (!enable_name.length())
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log_cmd_error("Unspecified enable wire\n");
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for (auto mod : design->selected_modules()) {
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Wire *enable_wire = mod->wire("\\" + enable_name);
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if (!enable_wire)
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log_cmd_error("Enable wire %s not found in module %s\n", enable_name.c_str(), mod->name.c_str());
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if (mode == State) {
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// for (auto cell : mod->selected_cells())
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// if (ct.cell_types.count(cell->type))
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changed += abstract_state(mod, {enable_wire, enable_pol});
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} else {
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changed += abstract_value(mod, {enable_wire, enable_pol});
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}
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}
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if (mode == State)
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log("Abstracted %d cells.\n", changed);
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else
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log("Abstracted %d values.\n", changed);
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} else if (mode == Initial) {
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for (auto mod : design->selected_modules()) {
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changed += abstract_init(mod);
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}
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log("Abstracted %d bits.\n", changed);
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} else {
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log_cmd_error("No mode selected, see help message\n");
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}
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}
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} AbstractPass;
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PRIVATE_NAMESPACE_END
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