mirror of https://github.com/YosysHQ/yosys.git
75 lines
1.5 KiB
Verilog
75 lines
1.5 KiB
Verilog
module reversed_gate (clk, ctrl, din, sel, dout);
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input clk;
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input [4:0] ctrl;
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input [15:0] din;
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input [3:0] sel;
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output reg [31:0] dout;
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always @(posedge clk)
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case ((({(32)-((ctrl)*(sel))})+(1))-(2))
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0:
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dout[1:0] <= din;
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1:
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dout[2:1] <= din;
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2:
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dout[3:2] <= din;
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3:
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dout[4:3] <= din;
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4:
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dout[5:4] <= din;
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5:
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dout[6:5] <= din;
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6:
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dout[7:6] <= din;
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7:
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dout[8:7] <= din;
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8:
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dout[9:8] <= din;
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9:
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dout[10:9] <= din;
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10:
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dout[11:10] <= din;
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11:
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dout[12:11] <= din;
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12:
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dout[13:12] <= din;
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13:
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dout[14:13] <= din;
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14:
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dout[15:14] <= din;
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15:
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dout[16:15] <= din;
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16:
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dout[17:16] <= din;
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17:
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dout[18:17] <= din;
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18:
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dout[19:18] <= din;
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19:
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dout[20:19] <= din;
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20:
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dout[21:20] <= din;
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21:
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dout[22:21] <= din;
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22:
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dout[23:22] <= din;
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23:
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dout[24:23] <= din;
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24:
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dout[25:24] <= din;
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25:
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dout[26:25] <= din;
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26:
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dout[27:26] <= din;
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27:
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dout[28:27] <= din;
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28:
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dout[29:28] <= din;
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29:
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dout[30:29] <= din;
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30:
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dout[31:30] <= din;
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31:
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dout[31:31] <= din;
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endcase
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endmodule
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