mirror of https://github.com/YosysHQ/yosys.git
142 lines
3.7 KiB
Verilog
142 lines
3.7 KiB
Verilog
`default_nettype none
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module latch_002_gate (dword, vect, sel, st);
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output reg [63:0] dword;
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input wire [7:0] vect;
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input wire [7:0] sel;
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input st;
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always @*
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case (|(st))
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1'b 1:
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case ((((8)*(sel)))+(0))
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0:
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dword[7:0] <= vect[7:0];
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1:
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dword[8:1] <= vect[7:0];
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2:
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dword[9:2] <= vect[7:0];
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3:
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dword[10:3] <= vect[7:0];
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4:
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dword[11:4] <= vect[7:0];
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5:
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dword[12:5] <= vect[7:0];
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6:
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dword[13:6] <= vect[7:0];
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7:
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dword[14:7] <= vect[7:0];
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8:
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dword[15:8] <= vect[7:0];
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9:
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dword[16:9] <= vect[7:0];
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10:
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dword[17:10] <= vect[7:0];
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11:
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dword[18:11] <= vect[7:0];
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12:
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dword[19:12] <= vect[7:0];
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13:
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dword[20:13] <= vect[7:0];
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14:
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dword[21:14] <= vect[7:0];
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15:
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dword[22:15] <= vect[7:0];
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16:
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dword[23:16] <= vect[7:0];
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17:
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dword[24:17] <= vect[7:0];
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18:
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dword[25:18] <= vect[7:0];
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19:
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dword[26:19] <= vect[7:0];
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20:
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dword[27:20] <= vect[7:0];
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21:
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dword[28:21] <= vect[7:0];
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22:
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dword[29:22] <= vect[7:0];
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23:
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dword[30:23] <= vect[7:0];
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24:
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dword[31:24] <= vect[7:0];
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25:
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dword[32:25] <= vect[7:0];
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26:
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dword[33:26] <= vect[7:0];
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27:
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dword[34:27] <= vect[7:0];
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28:
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dword[35:28] <= vect[7:0];
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29:
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dword[36:29] <= vect[7:0];
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30:
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dword[37:30] <= vect[7:0];
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31:
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dword[38:31] <= vect[7:0];
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32:
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dword[39:32] <= vect[7:0];
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33:
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dword[40:33] <= vect[7:0];
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34:
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dword[41:34] <= vect[7:0];
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35:
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dword[42:35] <= vect[7:0];
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36:
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dword[43:36] <= vect[7:0];
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37:
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dword[44:37] <= vect[7:0];
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38:
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dword[45:38] <= vect[7:0];
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39:
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dword[46:39] <= vect[7:0];
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40:
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dword[47:40] <= vect[7:0];
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41:
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dword[48:41] <= vect[7:0];
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42:
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dword[49:42] <= vect[7:0];
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43:
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dword[50:43] <= vect[7:0];
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44:
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dword[51:44] <= vect[7:0];
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45:
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dword[52:45] <= vect[7:0];
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46:
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dword[53:46] <= vect[7:0];
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47:
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dword[54:47] <= vect[7:0];
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48:
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dword[55:48] <= vect[7:0];
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49:
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dword[56:49] <= vect[7:0];
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50:
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dword[57:50] <= vect[7:0];
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51:
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dword[58:51] <= vect[7:0];
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52:
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dword[59:52] <= vect[7:0];
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53:
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dword[60:53] <= vect[7:0];
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54:
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dword[61:54] <= vect[7:0];
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55:
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dword[62:55] <= vect[7:0];
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56:
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dword[63:56] <= vect[7:0];
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57:
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dword[63:57] <= vect[7:0];
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58:
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dword[63:58] <= vect[7:0];
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59:
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dword[63:59] <= vect[7:0];
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60:
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dword[63:60] <= vect[7:0];
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61:
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dword[63:61] <= vect[7:0];
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62:
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dword[63:62] <= vect[7:0];
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63:
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dword[63:63] <= vect[7:0];
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endcase
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endcase
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endmodule
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