mirror of https://github.com/YosysHQ/yosys.git
42 lines
1.2 KiB
Plaintext
42 lines
1.2 KiB
Plaintext
# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
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# F7BMUX slower than F7AMUX
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# Inputs: I0 I1 S0
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# Outputs: O
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F7BMUX 1 1 3 1
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217 223 296
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# Inputs: I0 I1 S0
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# Outputs: O
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MUXF8 2 1 3 1
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104 94 273
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# CARRY4 + CARRY4_[ABCD]X
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# Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3
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# Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3
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CARRY4 3 1 10 8
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271 157 228 114 222 334 239 313
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536 494 592 580 482 598 584 642
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379 465 540 526 - 407 556 615
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- 445 520 507 - - 537 596
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- - 356 398 - - - 438
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- - - 385 - - - -
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340 433 512 508 223 400 523 582
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- 469 548 528 - 205 558 618
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- - 292 376 - - 226 330
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- - - 380 - - - 227
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# SLICEM/A6LUT
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# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
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# Outputs: DPO SPO
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RAM64X1D 4 1 15 2
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- - - - - - - 124 124 124 124 124 124 - -
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124 124 124 124 124 124 - - - - - - 124 - -
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# SLICEM/A6LUT + F7[AB]MUX
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# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
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# Outputs: DPO SPO
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RAM128X1D 5 1 17 2
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- - - - - - - - 314 314 314 314 314 314 292 - -
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347 347 347 347 347 347 296 - - - - - - - - - -
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