Dan Ravensloft 67b4ce06e0 intel: Map M9K BRAM only on families that have it ... This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM.		2019-07-23 18:11:11 +01:00
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achronix	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
anlogic	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
common	gen_lut to return correctly sized LUT mask	2019-07-16 12:45:29 -07:00
coolrunner2	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
easic	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ecp5	synth_ecp5: rename dram to lutram everywhere.	2019-07-16 20:45:12 +00:00
gowin	Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master	2019-04-22 09:09:27 +02:00
greenpak4	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ice40	Merge pull request #1184 from whitequark/synth-better-labels	2019-07-18 15:34:28 +02:00
intel	intel: Map M9K BRAM only on families that have it	2019-07-23 18:11:11 +01:00
sf2	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
xilinx	Merge pull request #1182 from koriakin/xc6s-bram	2019-07-11 12:55:35 -07:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00