mirror of https://github.com/YosysHQ/yosys.git
62 lines
1.4 KiB
Perl
Executable File
62 lines
1.4 KiB
Perl
Executable File
#!/usr/bin/perl -w
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#
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# Note: You might need to install the Verilog::VCD package using CPAN..
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use strict;
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use Data::Dumper;
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use Verilog::VCD qw(parse_vcd list_sigs);
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$| = 1;
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my $from_time = -1;
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my $to_time = -1;
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while (1)
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{
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if ($ARGV[0] eq '-f') {
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$from_time = +$ARGV[1];
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shift @ARGV;
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shift @ARGV;
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next;
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}
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if ($ARGV[0] eq '-t') {
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$to_time = +$ARGV[1];
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shift @ARGV;
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shift @ARGV;
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next;
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}
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last;
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}
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if ($#ARGV < 0) {
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print STDERR "\n";
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print STDERR "VCD2TXT - Convert VCD to tab-separated text file\n";
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print STDERR "\n";
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print STDERR "Usage: $0 [-f from_time] [-t to_time] input.vcd [<signal regex> ...]\n";
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print STDERR "\n";
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exit 1;
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}
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my $vcd = parse_vcd($ARGV[0]);
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for my $node (keys $vcd) {
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for my $net (@{$vcd->{$node}->{'nets'}}) {
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my $dump_this = $#ARGV == 0;
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for (my $i = 1; $i <= $#ARGV; $i++) {
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my $regex = $ARGV[$i];
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$dump_this = 1 if ($net->{"hier"} . "." . $net->{"name"}) =~ /$regex/;
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}
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next unless $dump_this;
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my $cached_value = "";
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for my $tv (@{$vcd->{$node}->{'tv'}}) {
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$cached_value = $tv->[1], next if $from_time >= 0 and +$tv->[0] < $from_time;
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next if $to_time >= 0 and +$tv->[0] > $to_time;
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printf "%s\t%s\t%s\t%s\n", $node, $from_time, $net->{"hier"} . "." . $net->{"name"}, $cached_value
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if $cached_value ne "" and $from_time >= 0 and +$tv->[0] > $from_time;
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printf "%s\t%s\t%s\t%s\n", $node, $tv->[0], $net->{"hier"} . "." . $net->{"name"}, $tv->[1];
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$cached_value = "";
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}
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}
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}
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