mirror of https://github.com/YosysHQ/yosys.git
344 lines
11 KiB
C++
344 lines
11 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 QuickLogic Corp.
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* Copyright 2020-2022 F4PGA Authors
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthQuickLogicPass : public ScriptPass {
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SynthQuickLogicPass() : ScriptPass("synth_quicklogic", "Synthesis for QuickLogic FPGAs") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_quicklogic [options]\n");
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log("This command runs synthesis for QuickLogic FPGAs\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module\n");
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log("\n");
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log(" -family <family>\n");
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log(" run synthesis for the specified QuickLogic architecture\n");
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log(" generate the synthesis netlist for the specified family.\n");
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log(" supported values:\n");
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log(" - pp3: PolarPro 3 \n");
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log(" - qlf_k6n10f: K6N10f\n");
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log("\n");
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log(" -nocarry\n");
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log(" do not use adder_carry cells in output netlist.\n");
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log("\n");
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log(" -nobram\n");
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log(" do not use block RAM cells in output netlist.\n");
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log("\n");
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log(" -bramtypes\n");
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log(" Emit specialized BRAM cells for particular address and data width\n");
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log(" configurations.\n");
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log("\n");
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log(" -blif <file>\n");
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log(" write the design to the specified BLIF file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -verilog <file>\n");
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log(" write the design to the specified verilog file. writing of an output\n");
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log(" file is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -abc\n");
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log(" use old ABC flow, which has generally worse mapping results but is less\n");
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log(" likely to have bugs.\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path;
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bool abc9, inferAdder, nobram, bramTypes;
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void clear_flags() override
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{
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top_opt = "-auto-top";
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blif_file = "";
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edif_file = "";
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verilog_file = "";
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currmodule = "";
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family = "pp3";
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abc9 = true;
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inferAdder = true;
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nobram = false;
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bramTypes = false;
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lib_path = "+/quicklogic/";
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}
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void set_scratchpad_defaults(RTLIL::Design *design) {
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lib_path = design->scratchpad_get_string("ql.lib_path", lib_path);
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if (lib_path.back() != '/')
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lib_path += "/";
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inferAdder = !design->scratchpad_get_bool("ql.nocarry", false);
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nobram = design->scratchpad_get_bool("ql.nobram", false);
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bramTypes = design->scratchpad_get_bool("ql.bramtypes", false);
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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string run_from, run_to;
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clear_flags();
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set_scratchpad_defaults(design);
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-family" && argidx+1 < args.size()) {
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family = args[++argidx];
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continue;
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}
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if (args[argidx] == "-blif" && argidx+1 < args.size()) {
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blif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-verilog" && argidx+1 < args.size()) {
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verilog_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-abc") {
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abc9 = false;
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continue;
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}
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if (args[argidx] == "-nocarry" || args[argidx] == "-no_adder") {
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inferAdder = false;
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continue;
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}
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if (args[argidx] == "-nobram" || args[argidx] == "-no_bram") {
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nobram = true;
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continue;
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}
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if (args[argidx] == "-bramtypes" || args[argidx] == "-bram_types") {
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bramTypes = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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if (family != "pp3" && family != "qlf_k6n10f")
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log_cmd_error("Invalid family specified: '%s'\n", family.c_str());
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if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) {
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log_warning("delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.\n");
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design->scratchpad_set_int("abc9.D", 41667); // 12MHz = 83.33.. ns; divided by two to allow for interconnect delay.
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}
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log_header(design, "Executing SYNTH_QUICKLOGIC pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() override
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{
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if (help_mode) {
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family = "<family>";
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}
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if (check_label("begin")) {
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std::string read_simlibs = stringf("read_verilog -lib -specify %scommon/cells_sim.v %s%s/cells_sim.v", lib_path.c_str(), lib_path.c_str(), family.c_str());
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if (family == "qlf_k6n10f") {
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read_simlibs += stringf(" %sqlf_k6n10f/brams_sim.v", lib_path.c_str());
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if (bramTypes)
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read_simlibs += stringf(" %sqlf_k6n10f/bram_types_sim.v", lib_path.c_str());
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}
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run(read_simlibs);
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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if (check_label("prepare")) {
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run("proc");
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run("flatten");
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if (help_mode || family == "pp3") {
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run("tribuf -logic", " (for pp3)");
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}
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run("deminout");
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run("opt_expr");
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run("opt_clean");
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run("check");
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run("opt -nodffe -nosdff");
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run("fsm");
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run("opt");
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run("wreduce");
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run("peepopt");
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run("opt_clean");
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run("share");
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}
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if (check_label("coarse")) {
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run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
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run("opt_expr");
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run("opt_clean");
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run("alumacc");
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run("pmuxtree");
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run("opt");
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run("memory -nomap");
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run("opt_clean");
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}
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if (check_label("map_bram", "(for qlf_k6n10f, skip if -no_bram)") && (help_mode || family == "qlf_k6n10f")) {
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run("memory_libmap -lib " + lib_path + family + "/libmap_brams.txt");
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run("ql_bram_merge");
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run("techmap -map " + lib_path + family + "/libmap_brams_map.v");
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run("techmap -autoproc -map " + lib_path + family + "/brams_map.v");
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run("techmap -map " + lib_path + family + "/brams_final_map.v");
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if (help_mode || bramTypes) {
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run("ql_bram_types");
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}
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}
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if (check_label("map_ffram")) {
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run("opt -fast -mux_undef -undriven -fine");
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run("memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block "
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"-attr syn_ramstyle=auto -attr syn_ramstyle=registers "
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"-attr syn_romstyle=auto -attr syn_romstyle=logic");
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run("opt -undriven -fine");
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}
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if (check_label("map_gates")) {
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if (inferAdder && family == "qlf_k6n10f") {
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run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v", "(unless -no_adder)");
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} else {
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run("techmap");
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}
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run("opt -fast");
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if (help_mode || family == "pp3") {
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run("muxcover -mux8 -mux4", "(for pp3)");
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}
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}
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if (check_label("map_ffs")) {
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run("opt_expr");
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if (help_mode) {
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run("shregmap -minlen <min> -maxlen <max>", "(for qlf_k6n10f)");
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run("dfflegalize -cell <supported FF types>");
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run("techmap -map " + lib_path + family + "/cells_map.v", "(for pp3)");
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}
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if (family == "pp3") {
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run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x");
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run("techmap -map " + lib_path + family + "/cells_map.v -map " + lib_path + family + "/ffs_map.v");
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run("opt_expr -mux_undef");
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} else if (family == "qlf_k6n10f") {
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run("shregmap -minlen 8 -maxlen 20");
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// FIXME: Apparently dfflegalize leaves around $_DLATCH_[NP]_ even if
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// not in the allowed set. As a workaround we put them in the allowed
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// set explicitly and map them later to $_DLATCHSR_[NP]NN_.
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run("dfflegalize -cell $_DFFSRE_?NNP_ 0 -cell $_DLATCHSR_?NN_ 0 -cell $_DLATCH_?_ 0" " -cell $_SDFFE_?N?P_ 0");
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}
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run("opt");
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}
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if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) {
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run("techmap -map " + lib_path + family + "/latches_map.v");
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if (abc9) {
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run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v");
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run("techmap -map " + lib_path + family + "/abc9_map.v");
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run("abc9 -maxlut 4 -dff");
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run("techmap -map " + lib_path + family + "/abc9_unmap.v");
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} else {
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run("abc -luts 1,2,2,4 -dress");
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}
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run("clean");
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}
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if (check_label("map_luts", "(for qlf_k6n10f)") && (help_mode || family == "qlf_k6n10f")) {
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if (abc9) {
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run("abc9 -maxlut 6");
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} else {
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run("abc -lut 6 -dress");
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}
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run("clean");
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run("opt_lut");
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}
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if (check_label("map_cells", "(for pp3)") && (help_mode || family == "pp3")) {
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run("techmap -map " + lib_path + family + "/lut_map.v");
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run("clean");
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run("opt_lut");
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}
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if (check_label("check")) {
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run("autoname");
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run("hierarchy -check");
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run("stat");
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run("check -noinit");
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}
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if (check_label("iomap", "(for pp3)") && (family == "pp3" || help_mode)) {
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run("clkbufmap -inpad ckpad Q:P");
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run("iopadmap -bits -outpad outpad A:P -inpad inpad Q:P -tinoutpad bipad EN:Q:A:P A:top");
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}
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if (check_label("finalize")) {
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if (help_mode || family == "pp3") {
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run("setundef -zero -params -undriven", "(for pp3)");
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}
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if (family == "pp3" || !edif_file.empty()) {
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run("hilomap -hicell logic_1 A -locell logic_0 A -singleton A:top", "(for pp3 or if -edif)");
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}
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run("opt_clean -purge");
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run("check");
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run("blackbox =A:whitebox");
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}
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if (check_label("blif", "(if -blif)")) {
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if (!blif_file.empty() || help_mode) {
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run(stringf("write_blif -attr -param %s %s", top_opt.c_str(), blif_file.c_str()));
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}
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}
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if (check_label("verilog", "(if -verilog)")) {
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if (!verilog_file.empty() || help_mode) {
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run(stringf("write_verilog -noattr -nohex %s", help_mode ? "<file-name>" : verilog_file.c_str()));
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}
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}
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}
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} SynthQuicklogicPass;
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PRIVATE_NAMESPACE_END
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