mirror of https://github.com/YosysHQ/yosys.git
291 lines
8.5 KiB
Plaintext
291 lines
8.5 KiB
Plaintext
read_verilog << EOT
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module dffe_00( input clk, en,
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input d1, output reg q1,
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);
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always @( negedge clk ) begin
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if ( ~en )
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q1 <= d1;
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end
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endmodule
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module dffe_01( input clk, en,
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input d1, output reg q1,
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);
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always @( negedge clk ) begin
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if ( en )
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q1 <= d1;
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end
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endmodule
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module dffe_10( input clk, en,
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input d1, output reg q1,
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);
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always @( posedge clk ) begin
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if ( ~en )
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q1 <= d1;
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end
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endmodule
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module dffe_11( input clk, en,
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input d1, output reg q1,
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);
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always @( posedge clk ) begin
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if ( en )
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q1 <= d1;
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end
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endmodule
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module dffe_wide_11( input clk, en,
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input [3:0] d1, output reg [3:0] q1,
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);
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always @( posedge clk ) begin
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if ( en )
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q1 <= d1;
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end
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endmodule
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EOT
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proc
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opt
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design -save before
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#------------------------------------------------------------------------------
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# Test -pos
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clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
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# falling edge clock flops don't get matched on -pos
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select -module dffe_00 -assert-count 0 t:\\pdk_icg
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select -module dffe_01 -assert-count 0 t:\\pdk_icg
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# rising edge clock flops do get matched on -pos
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select -module dffe_10 -assert-count 1 t:\\pdk_icg
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select -module dffe_11 -assert-count 1 t:\\pdk_icg
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# if necessary, EN is inverted, since the given ICG
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# is assumed to have an active-high EN
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select -module dffe_10 -assert-count 1 t:\$_NOT_
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select -module dffe_11 -assert-count 0 t:\$_NOT_
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# Extra credit: multi-bit FFs work fine as well
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select -module dffe_wide_11 -assert-count 1 t:\\pdk_icg
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#------------------------------------------------------------------------------
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# Test -neg
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design -load before
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clockgate -min_net_size 1 -neg pdk_icg ce:clkin:clkout -tie_lo scanen
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# falling edge clock flops do get matched on -neg
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select -module dffe_00 -assert-count 1 t:\\pdk_icg
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select -module dffe_01 -assert-count 1 t:\\pdk_icg
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# rising edge clock flops don't get matched on -neg
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select -module dffe_10 -assert-count 0 t:\\pdk_icg
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select -module dffe_11 -assert-count 0 t:\\pdk_icg
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# if necessary, EN is inverted, since the given ICG
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# is assumed to have an active-high EN
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select -module dffe_00 -assert-count 1 t:\$_NOT_
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select -module dffe_01 -assert-count 0 t:\$_NOT_
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#------------------------------------------------------------------------------
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# Same as first case, but on fine-grained cells
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design -load before
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techmap
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clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
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# falling edge clock flops don't get matched on -pos
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select -module dffe_00 -assert-count 0 t:\\pdk_icg
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select -module dffe_01 -assert-count 0 t:\\pdk_icg
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# falling edge clock flops do get matched on -pos
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select -module dffe_10 -assert-count 1 t:\\pdk_icg
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select -module dffe_11 -assert-count 1 t:\\pdk_icg
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# if necessary, EN is inverted, since the given ICG
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# is assumed to have an active-high EN
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select -module dffe_10 -assert-count 1 t:\$_NOT_
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select -module dffe_11 -assert-count 0 t:\$_NOT_
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# Extra credit: multi-bit FFs work fine as well
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select -module dffe_wide_11 -assert-count 1 t:\\pdk_icg
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#------------------------------------------------------------------------------
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design -load before
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clockgate -min_net_size 2 -neg pdk_icg ce:clkin:clkout -tie_lo scanen
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# No FF set sharing a (clock, clock enable) pair is large enough
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select -module dffe_00 -assert-count 0 t:\\pdk_icg
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select -module dffe_01 -assert-count 0 t:\\pdk_icg
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select -module dffe_10 -assert-count 0 t:\\pdk_icg
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select -module dffe_11 -assert-count 0 t:\\pdk_icg
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#------------------------------------------------------------------------------
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design -reset
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read_rtlil << EOT
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module \bad1
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wire input 1 \clk
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wire input 3 \d1
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wire input 2 \en
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wire output 4 \q1
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cell $dffe $auto$ff.cc:266:slice$27
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parameter \CLK_POLARITY 1
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parameter \EN_POLARITY 1
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parameter \WIDTH 1
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connect \CLK \clk
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connect \D \d1
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connect \EN 1'1
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connect \Q \q1
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end
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end
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module \bad2
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wire input 1 \clk
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wire input 3 \d1
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wire input 2 \en
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wire output 4 \q1
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cell $dffe $auto$ff.cc:266:slice$27
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parameter \CLK_POLARITY 1
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parameter \EN_POLARITY 1
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parameter \WIDTH 1
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connect \CLK 1'1
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connect \D \d1
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connect \EN \en
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connect \Q \q1
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end
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end
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EOT
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# Check we don't choke on constants
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clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
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select -module bad1 -assert-count 0 t:\\pdk_icg
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select -module bad2 -assert-count 0 t:\\pdk_icg
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#------------------------------------------------------------------------------
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# Regression test: EN is a bit from a multi-bit wire
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design -reset
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read_verilog << EOT
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module dffe_wide_11( input clk, input [1:0] en,
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input [3:0] d1, output reg [3:0] q1,
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);
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always @( posedge clk ) begin
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if ( en[0] )
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q1 <= d1;
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end
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endmodule
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EOT
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proc
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opt
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clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
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select -assert-count 1 t:\\pdk_icg
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#------------------------------------------------------------------------------
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design -load before
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clockgate -liberty clockgate.lib
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# rising edge ICGs
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select -module dffe_00 -assert-count 0 t:\\pos_small
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select -module dffe_01 -assert-count 0 t:\\pos_small
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select -module dffe_10 -assert-count 1 t:\\pos_small
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select -module dffe_11 -assert-count 1 t:\\pos_small
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# falling edge ICGs
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select -module dffe_00 -assert-count 1 t:\\neg_small
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select -module dffe_01 -assert-count 1 t:\\neg_small
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select -module dffe_10 -assert-count 0 t:\\neg_small
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select -module dffe_11 -assert-count 0 t:\\neg_small
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# and nothing else
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select -module dffe_00 -assert-count 0 t:\\pos_big
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select -module dffe_01 -assert-count 0 t:\\pos_big
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select -module dffe_10 -assert-count 0 t:\\pos_big
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select -module dffe_11 -assert-count 0 t:\\pos_big
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select -module dffe_00 -assert-count 0 t:\\pos_small_tielo
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select -module dffe_01 -assert-count 0 t:\\pos_small_tielo
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select -module dffe_10 -assert-count 0 t:\\pos_small_tielo
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select -module dffe_11 -assert-count 0 t:\\pos_small_tielo
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select -module dffe_00 -assert-count 0 t:\\neg_big
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select -module dffe_01 -assert-count 0 t:\\neg_big
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select -module dffe_10 -assert-count 0 t:\\neg_big
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select -module dffe_11 -assert-count 0 t:\\neg_big
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select -module dffe_00 -assert-count 0 t:\\neg_small_tielo
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select -module dffe_01 -assert-count 0 t:\\neg_small_tielo
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select -module dffe_10 -assert-count 0 t:\\neg_small_tielo
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select -module dffe_11 -assert-count 0 t:\\neg_small_tielo
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# if necessary, EN is inverted, since the given ICG
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# is assumed to have an active-high EN
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select -module dffe_10 -assert-count 1 t:\$_NOT_
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select -module dffe_11 -assert-count 0 t:\$_NOT_
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#------------------------------------------------------------------------------
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# test multiple liberty files to behave the same way
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design -load before
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clockgate -liberty clockgate_pos.lib -liberty clockgate_neg.lib
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# rising edge ICGs
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select -module dffe_00 -assert-count 0 t:\\pos_small
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select -module dffe_01 -assert-count 0 t:\\pos_small
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select -module dffe_10 -assert-count 1 t:\\pos_small
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select -module dffe_11 -assert-count 1 t:\\pos_small
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# falling edge ICGs
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select -module dffe_00 -assert-count 1 t:\\neg_small
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select -module dffe_01 -assert-count 1 t:\\neg_small
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select -module dffe_10 -assert-count 0 t:\\neg_small
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select -module dffe_11 -assert-count 0 t:\\neg_small
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# and nothing else
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select -module dffe_00 -assert-count 0 t:\\pos_big
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select -module dffe_01 -assert-count 0 t:\\pos_big
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select -module dffe_10 -assert-count 0 t:\\pos_big
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select -module dffe_11 -assert-count 0 t:\\pos_big
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select -module dffe_00 -assert-count 0 t:\\pos_small_tielo
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select -module dffe_01 -assert-count 0 t:\\pos_small_tielo
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select -module dffe_10 -assert-count 0 t:\\pos_small_tielo
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select -module dffe_11 -assert-count 0 t:\\pos_small_tielo
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select -module dffe_00 -assert-count 0 t:\\neg_big
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select -module dffe_01 -assert-count 0 t:\\neg_big
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select -module dffe_10 -assert-count 0 t:\\neg_big
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select -module dffe_11 -assert-count 0 t:\\neg_big
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select -module dffe_00 -assert-count 0 t:\\neg_small_tielo
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select -module dffe_01 -assert-count 0 t:\\neg_small_tielo
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select -module dffe_10 -assert-count 0 t:\\neg_small_tielo
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select -module dffe_11 -assert-count 0 t:\\neg_small_tielo
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# if necessary, EN is inverted, since the given ICG
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# is assumed to have an active-high EN
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select -module dffe_10 -assert-count 1 t:\$_NOT_
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select -module dffe_11 -assert-count 0 t:\$_NOT_
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#------------------------------------------------------------------------------
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design -load before
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clockgate -liberty clockgate.lib -dont_use pos_small -dont_use neg_small
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# rising edge ICGs
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select -module dffe_10 -assert-count 1 t:\\pos_big
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select -module dffe_11 -assert-count 1 t:\\pos_big
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# falling edge ICGs
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select -module dffe_00 -assert-count 1 t:\\neg_big
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select -module dffe_01 -assert-count 1 t:\\neg_big
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