mirror of https://github.com/YosysHQ/yosys.git
29 lines
510 B
Plaintext
29 lines
510 B
Plaintext
read_verilog <<EOF
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module test(clk, a, b, y);
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input wire clk;
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input wire [9:0] a;
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input wire [6:0] b;
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output wire [20:0] y;
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assign y = a * b;
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endmodule
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EOF
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booth
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sat -verify -set a 0 -set b 0 -prove y 0
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design -reset
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test_cell -s 1694091355 -n 100 -script booth_map_script.ys_ $mul
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design -reset
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read_verilog <<EOF
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module top(a,b,y);
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input wire [4:0] a;
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input wire [5:0] b;
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output wire [6:0] y;
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assign y = a * b;
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endmodule
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EOF
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synth -run :fine
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# test compatibility with alumacc
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equiv_opt -assert booth
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