mirror of https://github.com/YosysHQ/yosys.git
60 lines
1.0 KiB
Verilog
60 lines
1.0 KiB
Verilog
module testbench;
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reg clk;
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initial begin
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// $dumpfile("testbench.vcd");
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// $dumpvars(0, testbench);
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#5 clk = 0;
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repeat (10000) begin
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#5 clk = 1;
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#5 clk = 0;
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end
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$display("OKAY");
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end
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reg [2:0] dinA = 0;
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wire doutB,doutB1,doutB2;
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reg lat,latn,latsr = 0;
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top uut (
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.clk (clk ),
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.a (dinA[0] ),
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.pre (dinA[1] ),
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.clr (dinA[2] ),
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.b (doutB ),
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.b1 (doutB1 ),
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.b2 (doutB2 )
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);
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always @(posedge clk) begin
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#3;
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dinA <= dinA + 1;
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end
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always @*
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if ( clk )
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lat <= dinA[0];
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always @*
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if ( !clk )
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latn <= dinA[0];
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always @*
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if ( dinA[2] )
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latsr <= 1'b0;
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else if ( dinA[1] )
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latsr <= 1'b1;
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else if ( clk )
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latsr <= dinA[0];
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assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat));
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assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn));
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assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr));
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endmodule
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