mirror of https://github.com/YosysHQ/yosys.git
76 lines
1.6 KiB
Verilog
76 lines
1.6 KiB
Verilog
module testbench;
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reg clk;
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initial begin
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// $dumpfile("testbench.vcd");
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// $dumpvars(0, testbench);
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#5 clk = 0;
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repeat (10000) begin
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#5 clk = 1;
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#5 clk = 0;
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end
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$display("OKAY");
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end
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reg [2:0] dinA = 0;
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wire doutB,doutB1,doutB2,doutB3,doutB4;
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reg dff,ndff,adff,adffn,dffe = 0;
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top uut (
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.clk (clk ),
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.a (dinA[0] ),
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.pre (dinA[1] ),
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.clr (dinA[2] ),
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.b (doutB ),
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.b1 (doutB1 ),
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.b2 (doutB2 )
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);
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always @(posedge clk) begin
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#3;
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dinA <= dinA + 1;
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end
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always @( posedge clk, posedge dinA[1], posedge dinA[2] )
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if ( dinA[2] )
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dff <= 1'b0;
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else if ( dinA[1] )
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dff <= 1'b1;
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else
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dff <= dinA[0];
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always @( negedge clk, negedge dinA[1], negedge dinA[2] )
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if ( !dinA[2] )
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ndff <= 1'b0;
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else if ( !dinA[1] )
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ndff <= 1'b1;
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else
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ndff <= dinA[0];
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always @( posedge clk, posedge dinA[2] )
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if ( dinA[2] )
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adff <= 1'b0;
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else
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adff <= dinA[0];
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always @( posedge clk, negedge dinA[2] )
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if ( !dinA[2] )
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adffn <= 1'b0;
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else
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adffn <= dinA[0];
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always @( posedge clk )
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if ( dinA[2] )
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dffe <= dinA[0];
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assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
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assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
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assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
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//assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
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//assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
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endmodule
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