mirror of https://github.com/YosysHQ/yosys.git
92 lines
1.4 KiB
Verilog
92 lines
1.4 KiB
Verilog
module adff
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( input d, clk, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk, posedge clr )
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if ( clr )
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q <= 1'b0;
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else
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q <= d;
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endmodule
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module adffn
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( input d, clk, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk, negedge clr )
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if ( !clr )
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q <= 1'b0;
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else
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q <= d;
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endmodule
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module dffsr
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( input d, clk, pre, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk, posedge pre, posedge clr )
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if ( clr )
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q <= 1'b0;
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else if ( pre )
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q <= 1'b1;
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else
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q <= d;
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endmodule
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module ndffnsnr
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( input d, clk, pre, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( negedge clk, negedge pre, negedge clr )
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if ( !clr )
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q <= 1'b0;
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else if ( !pre )
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q <= 1'b1;
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else
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q <= d;
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endmodule
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module top (
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input clk,
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input clr,
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input pre,
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input a,
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output b,b1,b2,b3
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);
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dffsr u_dffsr (
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.clk (clk ),
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.clr (clr),
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.pre (pre),
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.d (a ),
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.q (b )
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);
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ndffnsnr u_ndffnsnr (
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.clk (clk ),
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.clr (clr),
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.pre (pre),
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.d (a ),
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.q (b1 )
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);
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adff u_adff (
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.clk (clk ),
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.clr (clr),
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.d (a ),
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.q (b2 )
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);
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adffn u_adffn (
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.clk (clk ),
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.clr (clr),
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.d (a ),
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.q (b3 )
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);
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endmodule
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